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US 8,912,602 B2Granted
FinFETs and methods for forming the same
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsYu-Rung Hsu, Chen-Hua Yu, Chen-Nan Yeh
Life of this patent
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Abstract
A Fin field effect transistor includes a fin disposed over a substrate. A gate is disposed over a channel portion of the fin. A source region is disposed at a first end of the fin. A drain region is disposed at a second end of the fin. The source region and the drain region are spaced from the substrate by at least one air gap.
Claims20
A Fin field effect transistor (FinFET) comprising:
- a fin disposed over a substrate;
- a gate disposed over a channel portion of the fin, wherein the gate comprises:
- a gate dielectric layer;
- and
- a gate electrode layer over the gate dielectric layer;
- a source region disposed at a first end of the fin;
- a drain region disposed at a second end of the fin, wherein the source region and the drain region are spaced from the substrate by at least one air gap;
- a dielectric layer for insulating the gate from the substrate, wherein the gate dielectric layer contacts a portion of the dielectric layer;
- and
- a porous silicon region between the substrate and the fin.
7 more elements
A Fin field effect transistor (FinFET) comprising:
- a fin disposed over a substrate;
- a gate disposed over a channel portion of the fin, wherein the gate comprises:
- a gate dielectric layer;
- and
- a gate electrode layer over the gate dielectric layer;
- a source region disposed at a first end of the fin;
- a drain region disposed at a second end of the fin, wherein the source region and the drain region are spaced from the substrate by at least one air gap;
- and
- a dielectric layer for insulating the gate from the substrate, wherein the gate dielectric layer contacts a portion of the dielectric layer, and wherein the dielectric layer does not extend over a portion of the substrate beneath the fin.
6 more elements
A semiconductor device comprising:
- a plurality of fin field effect transistors (FinFETs), wherein each FinFET comprises:
- a fin over a substrate;
- a porous silicon region between the substrate and the fin;
- a gate over a channel portion of the fin, wherein the gate comprises:
- a gate dielectric layer;
- and
- a gate electrode layer over the gate dielectric layer;
- a source region at a first end of the fin;
- and
- a drain region at a second end of the fin, wherein the source region and the drain region are spaced from the substrate by at least one air gap which extends under less than an entirety of the gate;
- an isolation feature separating one of the plurality of FinFETs from another of the plurality of FinFETs;
- and
- a dielectric layer for insulating the gate from the substrate, wherein the gate dielectric layer contacts a portion of the dielectric layer.
10 more elements
Dependencies are inferred from the claim text.