Integrated circuit structure and method for protection from damage to gate dielectric

An integrated circuit device comprising a plurality of common-gated dual-thickness dielectric MOSFETs, comprising:

• a semiconductor substrate;
• a first common-gated dual-thickness dielectric MOSFET, comprising:
• a first protective device comprising a first gate dielectric having a first thickness and formed over a first channel region,
• a first MOSFET comprising a second gate dielectric thicker than the first gate dielectric and formed over a second channel region, and
• a first common gate electrode serving as a gate electrode of the first protective device and as a gate electrode of the first MOSFET;
• and
• second common-gated dual-thickness dielectric MOSFET, comprising:
• a second protective device comprising a third gate dielectric having a third thickness and formed over a third channel region,
• a second MOSFET comprising a fourth gate dielectric thicker than the third gate dielectric and formed over a fourth channel region, and
• a second common gate electrode serving as a gate electrode of the second protective device and as a gate electrode of the second MOSFET.

An integrated circuit device comprising:

• a semiconductor substrate;
• a first device region and a second device region formed on the semiconductor substrate;
• a gate dielectric layer formed over the second device region;
• and
• a common electrode formed over the first and second device regions, the common electrode serving as a transistor gate electrode over the gate dielectric in the second device region, and the first device region providing a discharge path from the common electrode to the substrate, the discharge path having a lower resistance than a tunnel path through the gate dielectric layer over the second device region,
• wherein the first device region is configured to protect the second device region during fabrication of the second device region and is not configured as a final functional device.

A method of forming an integrated circuit device comprising a common-gated dual-oxide MOSFET, comprising:

• providing a semiconductor substrate;
• forming a first gate dielectric having a first thickness over a first channel region;
• forming a second gate dielectric thicker than the first gate dielectric over a second channel region;
• depositing a common gate electrode layer and masking the gate electrode layer;
• plasma etching the masked gate electrode layer to form a common gate electrode over the first and second channel regions;
• and
• conducting a first current through the first gate dielectric and a second current through the second gate dielectric during plasma etching, the first current being higher than the second current in absolute value.