Crack deflector structure for improving semiconductor device robustness against saw-induced damage

A process of forming an integrated circuit, comprising the steps of:

• providing a substrate, said substrate including a scribeline region adjacent to an area defined for said integrated circuit;
• forming a pre-metal dielectric (PMD) layer on a top surface of said substrate;
• forming a continuous contact in said PMD layer in a region defined for a crack deflecting structure, said crack deflecting structure region being located at a perimeter of said integrated circuit adjacent to said scribeline region, and such that said continuous contact directly connects to said substrate;
• forming a first IMD layer on a top surface of said PMD layer;
• forming a continuous first metal line in said first IMD layer in said crack deflecting structure region, such that said continuous first metal line connects to said continuous contact and does not overhang an exterior edge of said continuous contact;
• forming a first ILD layer on a top surface of said first IMD layer;
• forming a continuous first via in said first ILD layer in said crack deflecting structure region, such that said continuous first via connects to said continuous first metal line;
• forming a continuous second metal line in said first ILD layer in said crack deflecting structure region, such that said continuous second metal line connects to said continuous first via and does not overhang an exterior edge of said continuous first via;
• forming a second ILD layer on a top surface of said first ILD layer;
• forming a continuous second via in said second ILD layer in said crack deflecting structure region, such that said continuous second via connects to said continuous second metal line;
• and
• forming a continuous third metal line in said second ILD layer in said crack deflecting structure region, such that said continuous third metal line connects to said continuous second via and does not overhang an exterior edge of said continuous second via;
• such that at least one of the following conditions exists:
• said continuous first via is recessed from an exterior edge of said continuous first metal line;
• and
• said continuous second via is recessed from an exterior edge of said continuous second metal line;
• forming a second continuous contact in said PMD layer in a region defined for a second crack deflecting structure, said second crack deflecting structure region being located between said first crack deflecting structure and said area defined for said integrated circuit, and such that said second continuous contact directly connects to said substrate;
• forming a second continuous first metal line in said first IMD layer in said second crack deflecting structure region, such that said second continuous first metal line connects to said second continuous contact and does not overhang an exterior edge of said second continuous contact;
• forming a second continuous first via in said first ILD layer in said second crack deflecting structure region, such that said second continuous first via connects to said second continuous first metal line;
• forming a second continuous second metal line in said first ILD layer in said second crack deflecting structure region, such that said second continuous second metal line connects to said second continuous first via and does not overhang an exterior edge of said second continuous first via;
• forming a second continuous second via in said second ILD layer in said second crack deflecting structure region, such that said second continuous second via connects to said second continuous second metal line;
• and
• forming a second continuous third metal line in said second ILD layer in said second crack deflecting structure region, such that said second continuous third metal line connects to said second continuous second via and does not overhang an exterior edge of said second continuous second via;
• such that at least one of the following conditions exists:
• said second continuous first via is recessed from an exterior edge of said second continuous first metal line;
• and
• said second continuous second via is recessed from an exterior edge of said second continuous second metal line;
• forming a third continuous contact in said PMD layer in a region defined for a chemical impurity barrier structure, said chemical impurity barrier structure region being located on between said second crack deflecting structure and said area defined for said integrated circuit, and such that said third continuous contact directly connects to said substrate;
• forming a third continuous first metal line in said first IMD layer in said chemical impurity barrier region, such that said third continuous first metal line connects to said third continuous contact
• forming a third continuous first via in said first ILD layer in said chemical impurity barrier region, such that said third continuous first via connects to said third continuous first metal line;
• forming a third continuous second metal line in said first ILD layer in said chemical impurity barrier region, such that said third continuous second metal line connects to said third continuous first via;
• forming a third continuous second via in said second ILD layer in said chemical impurity barrier, such that said third continuous second via connects to said third continuous second metal line;
• and
• forming a third continuous third metal line in said second ILD layer in said chemical impurity barrier region, such that said third continuous third metal line connects to said third continuous second via.