Dual epitaxial integration for FinFETS

A dual epitaxial integration process for FinFET devices comprising:

• forming a first plurality of fins on a semiconductor substrate;
• forming a first plurality of gates with each gate of the first plurality of gates wrapping around at least one of the fins of the first plurality of fins, the first plurality of fins and first plurality of gates being for N-type FinFET devices (NFETs);
• forming a second plurality of fins on the semiconductor substrate;
• forming a second plurality of gates with each gate of the second plurality of gates wrapping around at least one of the fins of the second plurality of fins, the second plurality of fins and second plurality of gates being for P-type FinFET devices (PFETs);
• depositing a first layer of a hard mask material selected from the group consisting of titanium nitride, tungsten nitride, tantalum nitride, amorphous carbon and titanium carbide over the NFETs and PFETs;
• depositing a second layer of a hard mask material selected from the group consisting of silicon oxide and silicon nitride over the first layer of hard mask material;
• removing the first and second layers of hard mask material from one of the NFETs and PFETs and avoiding removing the first and second layers of hard mask material from the other of the NFETs and PFETs;
• epitaxially depositing a first source and drain material on the fins of the one of the NFETs and PFETs;
• removing the second layer of hard mask material from the other of the NFETs and the PFETs;
• depositing a third layer of a hard mask material selected from the group consisting of titanium nitride, tungsten nitride, tantalum nitride, amorphous carbon and titanium carbide over the NFETs and PFETs;
• depositing a fourth layer of a hard mask material selected from the group consisting of silicon oxide and silicon nitride over the third layer of hard mask material;
• removing the third and fourth layers of the hard mask material from the other of the NFETs and PFETs;
• epitaxially depositing a second source and drain material on the fins of the other of the NFETs and PFETs;
• and
• removing the third and fourth layers of the hard mask material from the one of the NFETs and PFETs.