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US 8,896,339 B2Granted
Method for testing semiconductor wafer
AssigneeMitsubishi Electric Corporation
InventorJun Takaso
Life of this patent
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Abstract
A semiconductor wafer includes semiconductor chips divided by a dicing line, one of the semiconductor chips including terminals of an identical potential; a wiring located on the dicing line, and electrically connecting the terminals to each other; and a pad electrically connected through the wiring to the terminals, wherein the pad is located entirely on the semiconductor chip and is not present on the dicing line.
Claims2
A method for testing a semiconductor wafer, wherein
- the semiconductor wafer comprises:
- a plurality of semiconductor chips within the semiconductor wafer and respectively separated from each other by a dicing line, wherein a first semiconductor chip of the plurality of semiconductor chips includes a plurality of terminals;
- a first wiring located partially on the dicing line and partially on the first semiconductor chip, wherein the first wiring electrically connects the plurality of terminals to each other so that all of the terminals have the same potential;
- and
- a plurality of pads, wherein
- each pad is electrically connected by a respective second wiring to a respective terminal,
- each of the pads is located entirely on the first semiconductor chip, and
- none of the pads is located on the dicing line:
- and
- the method comprises simultaneously applying an identical potential to the plurality of terminals by contacting a probe to only one of the pads of the plurality of pads.
7 more elements
A method for testing a semiconductor wafer, wherein
- the semiconductor wafer comprises:
- a plurality of semiconductor chips within the semiconductor wafer and respectively separated from each other by a dicing line, wherein a first semiconductor chip of the plurality of semiconductor chips includes a plurality of terminals;
- a first wiring located partially on the dicing line and partially on the first semiconductor chip, wherein the first wiring electrically connects the plurality of terminals to each other so that all of the terminals have the same potential;
- and
- a single pad, wherein
- the single pad is electrically connected by a second wiring to one of the terminals of the plurality of terminals, and
- the single pad is located entirely on the first semiconductor chip and not on any part of the dicing line;
- and
- the method comprises simultaneously applying an identical potential to the plurality of terminals by contacting a probe to the single pad.
6 more elements
Dependencies are inferred from the claim text.