Apparatus and method for source side implantation after spacer formation to reduce short channel effects in metal oxide semiconductor field effect transistors

A metal oxide semiconductor field effect transistor (MOSFET) comprising:

• a semiconductor substrate;
• a gate stack formed above said semiconductor substrate wherein said gate stack comprises a control gate that is formed from a first material and a floating gate that is formed from a second material;
• and
• a source side sidewall spacer formed on a source side of said gate stack wherein the effective channel length of said MOSFET extends from an outer surface of a drain side sidewall spacer formed on said drain side to an outer surface of said source side sidewall spacer formed on said source side and wherein said semiconductor substrate is free of n-type dopants in portions of said substrate underneath and directly contacting said source side sidewall spacer and said drain side sidewall spacer wherein the respective doping for an associated source and an associated drain are formed outside of the outside edges of said source and drain side sidewall spacers and does not extend within the outside edges and extends to a surface of the substrate that is coplanar with portions of the substrate that interface the gate stack wherein said control gate is fabricated with a first p-type base polysilicon material and wherein said floating gate adjacent to the control gate is fabricated with a second materially different p-type base polysilicon material and formed under separated by said dielectric layer.

A method for reducing short channel effects in a metal oxide semiconductor field effect transistor (MOSFET) comprising:

• forming a semiconductor substrate;
• forming a gate stack on said semiconductor substrate wherein said gate stack comprises a control gate that is formed from a first material and a floating gate that is formed from a second material;
• forming a drain side sidewall spacer on a drain side of said gate stack;
• forming a source side sidewall spacer on a source side of said gate stack;
• forming a source region in said semiconductor substrate on said source side by aligning said source region with said source side sidewall spacer;
• and
• forming a drain region in said semiconductor substrate in said drain side by aligning said drain region with said drain side sidewall spacer,
• wherein an effective channel length between said source region and said drain region is defined by the alignment of an outer surface of said source side sidewall spacer with said source region and the alignment of an outer surface of said drain side sidewall spacer with said drain region and wherein said semiconductor substrate is free of n-type dopants in portions of said substrate underneath and directly contacting said source side sidewall spacer and said drain side sidewall spacer and the respective doping for an associated source and an associated drain are formed outside of the outside edges of said source and drain side sidewall spacers and does not extend within the outside edges and extends to a surface of the substrate that is coplanar with portions of the substrate that interface the gate stack wherein said control gate is fabricated with a first p-type base polysilicon material and wherein said floating gate adjacent to the control gate is fabricated with a second materially different p-type base polysilicon material and separated by said dielectric layer.

In a non-volatile memory comprising at least one array of memory cells, wherein each of the memory cells comprise a source, a control gate, and a drain, and is capable of storing at least one bit, a method for manufacturing said array of memory cells, comprising:

• forming a semiconductor substrate;
• forming a plurality of gate stacks on said semiconductor substrate wherein said gate stacks comprises a control gate that is formed from a first material and a floating gate that is formed from a second material;
• forming drain regions in said semiconductor substrate on drain sides of each of said plurality of gate stacks;
• forming source regions in said semiconductor substrate;
• forming sidewall spacers on drain sides of each of said plurality of gate stacks;
• forming sidewall spacers on source sides of each of said plurality of gate stacks;
• and
• offsetting source regions from source side edges of said plurality of gate stacks by using said sidewall spacers to block implantation of said source regions to extend the effective channel lengths between said source regions and said drain regions of each of said array of memory cells,
• wherein said effective channel lengths extend from outer surfaces of said drain side sidewall spacers formed on said drain sides to outer surfaces of said source side sidewall spacers formed on said source sides and wherein said semiconductor substrate is free of n-type dopants in portions of said substrate underneath and directly contacting said source side sidewall spacers and said drain side sidewall spacers wherein the respective doping for an associated source and an associated drain are formed outside of the outside edges of said source and drain side sidewall spacers and does not extend within the outside edges and extends to a surface of the substrate that is coplanar with portions of the substrate that interface the gate stack wherein said control gate is fabricated with a first p-type base polysilicon material and wherein said floating gate adjacent to the control gate is fabricated with a second materially different p-type base polysilicon material and separated by said dielectric layer.