Semiconductor wafer plating bus and method for forming
AssigneeFreescale Semiconductor, Inc.
InventorTrent S. Uehling
Life of this patent
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Abstract
A semiconductor wafer includes a die, an edge seal, a bond pad, a plating bus, and trace. The die is adjacent to a saw street. The edge seal is along a perimeter of the die and includes a conductive layer formed in a last interconnect layer of the die. The bond pad is formed as part of metal deposition layer above the last interconnect layer or part of the last interconnect layer. The plating bus is within the saw street. The trace is connected to the bond pad and to the plating bus (1) over the edge seal, insulated from the edge seal, and formed in the metal deposition layer or (2) through the edge seal and insulated from the edge seal.
Claims8
A method of forming a semiconductor die, comprising:
- forming the semiconductor die on a semiconductor wafer using a plurality of interconnect layers;
- using the plurality of interconnect layers to form an edge seal around the die;
- using one of a group consisting of a metal deposition layer and a last interconnect layer of the plurality of interconnect layers to form a bond pad on the die;
- forming a plating bus within a saw street, wherein the edge seal is adjacent to the saw street;
- and
- forming a trace using one of a group consisting of the metal deposition layer and one of the plurality of interconnect layers to couple the bond pad to the plating bus.
A method of plating a bond pad of a semiconductor die on a wafer having a plurality of semiconductor die, comprising:
- forming the die using a plurality of interconnect layers;
- forming a plating bus within a saw street, wherein the die is adjacent the saw street;
- forming a bond pad on the die;
- forming a trace to electrically couple the bond pad to the plating bus;
- plating the bond pad by immersing the wafer in a plating solution and applying a voltage to the plating bus.
Dependencies are inferred from the claim text.