Time-interleaved multi-modulus frequency divider
AssigneeMassachusetts Institute of Technology
InventorMatthew C. Guyton
Life of this patent
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Abstract
Described are a multi-modulus frequency divider and event counter that are based on time-interleaved signals generated from a received signal. For the frequency divider, each time-interleaved clock signal generated from a received clock signal is provided to a bit counter and the output signal from each bit counter is provided to a multiplexer. A multiplexer selection module controls over time which one of the output signals from the bit counters is presented at the output of the multiplexer. The transition frequency of the bits in the time-interleaved clock signals allows various circuit components such as the bit counters to be implemented as CMOS components. Thus the frequency divider is more power-efficient than conventional frequency divider circuits operating at high clock frequencies.
Claims23
A multi-modulus frequency divider, comprising:
- a time-interleaved multi-clock generator configured to generate a plurality of time-interleaved clock signals from a received clock signal;
- a plurality of bit counters each having an input in communication with the time-interleaved multi-clock generator to receive a respective one of the time-interleaved clock signals, each of the bit counters having an output to provide a counter output signal;
- a multiplexer having a plurality of multiplexer inputs each in communication with the output of a respective one of the bit counters, the multiplexer having a multiplexer output;
- and
- a multiplexer selection module in communication with the multiplexer and generating a selection signal based on a divider ratio, the selection signal controlling which one of the counter output signals at the multiplexer inputs is provided to the multiplexer output.
A method of generating a frequency-divided signal, the method comprising:
- generating a plurality of time-interleaved clock signals based on a reference clock signal, each of the time-interleaved clock signals having a frequency that is less than a frequency of the reference signal;
- generating a divided time-interleaved clock signal from each of the time-interleaved clock signals;
- providing a first one of the divided time-interleaved clock signals at a circuit output during a first output cycle;
- and
- providing a second one of the divided time-interleaved clock signals at the circuit output during a second output cycle, wherein the second one of the divided time-interleaved clock signals is determined from the plurality of divided time-interleaved clock signals according to a divider ratio.
A time-interleaved event counter, comprising:
- a demultiplexer having a demultiplexer input to receive an event signal having a plurality of events and generating at a plurality of demultiplexer outputs a plurality of time-interleaved event signals during a counting interval, each of the events in the event signal being distributed into only one of the time-interleaved event signals;
- a plurality of bit counters each having a counter input in communication with one of the demultiplexer outputs to receive a respective one of the time-interleaved event signals and each having a counter output to provide a count value;
- and
- a count sum module having a plurality of inputs each in communication with a respective one of the counter outputs and having an output to provide a total count value according to a sum of the count values at an expiration of the counting interval.
A method of counting events, the method comprising:
- generating a plurality of time-interleaved event signals from an event signal, where each of the events in the event signal is included in only one of the time-interleaved event signals;
- for each of the time-interleaved event signals, counting a number of events during a counting interval to generate a count value;
- and
- determining a number of events in the event signal during the counting interval as a sum of the count values after expiration of the counting interval.
Dependencies are inferred from the claim text.