Latch-up prevention structure and method for ultra-small high voltage tolerant cell

An integrated circuit, comprising:

• an input and/or output pad;
• a HVNW control circuit electrically coupled to a first voltage supply;
• a floating high-voltage n-well (HVNW) connected to the input and/or output pad through a P+ in the floating HVNW and to the HVNW control circuit through an N+ in the floating HVNW;
• a low-voltage n-well (LVNW) connected to a second voltage supply through an N+ in the LVNW;
• and
• a guard-ring HVNW electrically coupled to the HVNW control circuit;
• wherein the first voltage supply has higher voltage level than the second voltage supply, the guard-ring HVNW is inserted in between the floating HVNW and LVNW to prevent a latch-up path between the P+ in the floating HVNW and the N+ in the LVNW by using the HVNW control circuit that controls the guard-ring HVNW's voltage level that is matched by the floating HVNW's voltage level.

An integrated circuit, comprising:

• an input and/or output pad;
• a floating high-voltage n-well (HVNW) connected to the input and/or output pad through a P+ in the floating HVNW and also connected to a first voltage supply;
• a low-voltage n-well (LVNW) connected to a second voltage supply through a N+ in the LVNW;
• a HVNW control circuit;
• and
• a guard-ring HVNW;
• wherein the first voltage supply has higher voltage level than the second voltage supply, guard-ring HVNW is inserted in between the floating HVNW and LVNW to prevent a latch-up path between a P+ in HVNW and N+ in LVNW by using the HVNW control circuit that controls the guard-ring HVNW's voltage level that is matched by the floating HVNW's voltage level, the HVNW control circuit is connected to a bulk and a gate of an I/O PMOS driver, and the bulk of the I/O PMOS driver is also the floating HVNW.