Fin-type field effect transistor
AssigneeUnited Microelectronics Corp.
InventorsChih-Jung Wang, Tong-Yu Chen
Life of this patent
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Abstract
A fin-type field effect transistor including at least one fin-type semiconductor structure, a gate strip and a gate insulating layer is provided. The fin-type semiconductor structure is doped with a first type dopant and has a block region with a first doping concentration and a channel region with a second doping concentration. The first doping concentration is larger than the second doping concentration. The blocking region has a height. The channel region is configured above the blocking region. The gate strip is substantially perpendicular to the fin-type semiconductor structure and covers above the channel region. The gate insulating layer is disposed between the gate strip and the fin-type semiconductor structure.
Claims7
A fin-type field effect transistor, comprising:
- a first fin-type semiconductor structure and a second fin-type semiconductor structure, each of the first and the second fin-type semiconductor structures doped with a first type dopant and having a channel region and a blocking region, wherein the blocking region has a first doping concentration, the channel region has a second doping concentration smaller than the first doping concentration, and the channel region is defined above the blocking region, the first and the second fin-type semiconductor structures having the same height equal to the sum of a height of the channel region and a height of the blocking region, wherein the blocking regions of the first and the second fin-type semiconductor structures have different heights;
- a gate strip, substantially parallel to the first and the second fin-type semiconductor structures and covering on the channel regions;
- a gate insulating layer, disposed between the gate strip and the first and the second fin-type semiconductor structures;
- a semiconductor substrate with a plurality of trenches substantially parallel to each other, wherein each of the first and the second fin-type semiconductor structures is defined between the adjacent trenches;
- and
- a plurality of insulating structures configured within the trenches and the gate strip configured thereon, wherein the top surface of the blocking region is higher than the top surface of each insulating structure, wherein a bottom most surface of the blocking region is coplanar to the top surface of the insulating structures.
Dependencies are inferred from the claim text.