Memory arrays with rows of memory cells coupled to opposite sides of a control gate
AssigneeMicron Technology, Inc.
InventorsRoger W. Lindsay, Lyle Jones
Life of this patent
Estimating the term…
Abstract
A memory array includes a control gate, where every memory cell coupled to a first side of the control gate is within a first row of memory cells and every memory cell coupled to a second side of the control gate is within a second row of memory cells, and where the first row of memory cells is successively adjacent to the second row of memory cells. The memory array also includes alternating first and second bit lines, where each of the memory cells of the first row of memory cells is coupled to a respective one of the first bit lines, where each of the memory cells of the second row of memory cells is coupled to a respective one of the second bit lines, and wherein the first bit lines are different from the second bit lines.
Claims21
An array of memory cells, comprising:
- first and second successively adjacent rows of memory cells on a first row of pillars, each pillar of the first row of pillars having a memory cell of the first row of memory cells and a memory cell of the second row of memory cells on opposite sides thereof;
- third and fourth successively adjacent rows of memory cells on a second row of pillars, the second row of pillars being successively adjacent the first row of pillars, each pillar of the second row of pillars having a memory cell of the third row of memory cells and a memory cell of the fourth row of memory cells on opposite sides thereof, wherein the second and third rows of memory cells are successively adjacent to each other;
- a control gate, wherein all of the memory cells of the second row of memory cells are coupled to one side of the control gate and all of the memory cells of the third row of memory cells are coupled to an opposite side of the control gate;
- and
- alternating first and second bit lines, wherein each of the memory cells of the second row of memory cells is coupled to a respective one of the first bit lines and each of the memory cells of the third row of memory cells is coupled to a respective one of the second bit lines, and wherein at least one of the second bit lines is between a pair of the first bit lines and is successively adjacent to the first bit lines of the pair of first bit lines.
An array of memory cells, comprising:
- a control gate, wherein every memory cell coupled to a first side of the control gate is within a first row of memory cells and every memory cell coupled to a second side of the control gate is within a second row of memory cells, and wherein the first row of memory cells is successively adjacent to the second row of memory cells;
- and
- alternating first and second bit lines, wherein each of the memory cells of the first row of memory cells is coupled to a respective one of the first bit lines, wherein each of the memory cells of the second row of memory cells is coupled to a respective one of the second bit lines, and wherein the first bit lines are different from the second bit lines;
- wherein the memory cells of the first row of memory cells are respectively formed on sides of pillars of a first row of pillars and the memory cells of the second row of memory cells are respectively formed on sides of pillars of a second row of pillars.
A memory array, comprising:
- at least three pillars;
- a memory cell on each of the at least three pillars;
- a word line commonly coupled to the memory cells on the at least three pillars;
- a first bit line coupled to the memory cell on a first pillar of the at least three pillars;
- a second bit line coupled to the memory cell on a second pillar of the at least three pillars;
- and
- a third bit line coupled to the memory cell on a third pillar of the at least three pillars;
- wherein the memory cells on the first and second pillars of the at least three pillars are coupled to a same side of the word line and the memory cell on the third pillar of the at least three pillars is coupled to an opposite side of the word line;
- and
- wherein the third bit line is between the first and second bit lines, the third bit line is successively adjacent to the first bit line, and the second bit line is successively adjacent to the third bit line.
Dependencies are inferred from the claim text.