Layout methods of integrated circuits having unit MOS devices

A semiconductor structure comprising:

• a first array;
• a second array substantially identical to the first array, wherein the first and the second arrays each comprise identical unit metal-oxide-semiconductor (MOS) devices arranged in a plurality of rows and a plurality of columns, and wherein each of the unit MOS devices in the first and the second arrays comprises:
• an active region laid out in a first direction, wherein the first direction is selected from a row direction and a column direction;
• and
• a gate electrode laid out in a second direction perpendicular to the first direction, wherein the second direction is selected from the row direction and the column direction;
• a first plurality of contacts in the first array;
• a second plurality of contacts in the second array, wherein the first plurality of contacts and the second plurality of contacts have different layouts;
• a first unit MOS device in the first array;
• a second unit MOS device in the first array, wherein active regions of the first and the second unit MOS devices have different conductivity types;
• a third unit MOS device and a fourth unit MOS device in a same column of the first array and next to each other;
• a first contact electrically connecting sources of the third and the fourth unit MOS devices;
• and
• a second contact electrically connecting drains of the third and the fourth unit MOS devices, wherein gates of the third and the fourth unit MOS devices are electrically connected.