Using a single mask for various design configurations
AssigneeAltera Corporation
InventorsLawrence David Landis, Richard Price
Life of this patent
Estimating the term…
Abstract
Techniques and design methodologies for using a single mask set to create devices of different sizes are disclosed. A mask with a plurality of tiles is disclosed. Each of the tiles has a number of fixed resource blocks, multiple logic blocks and is surrounded by a scribe region. The tiles may be connected to one or more adjacent tiles through interconnect lines that enable the fixed resource blocks and logic blocks in one tile to communicate with the fixed resource and logic blocks in an adjacent tile. The mask set may be used to produce devices of different sizes. Using a mask set that can handle a variety of design sizes with varying resources may in turn reduce mask cost.
Claims20
A die, comprising:
- a plurality of tiles, each tile forming a layer of the die, the tiles comprising,
- a plurality of fixed resource blocks,
- a plurality of logic blocks, wherein a tile is configurable to couple to one or more adjacent tiles through interconnect lines routed through a die seal defined within a scribe region surrounding the plurality of tiles, the interconnect lines configured for communicating with the plurality of fixed resource blocks and the plurality of logic blocks in the one or more adjacent tiles, the interconnect lines traversing through at least one opening within the die seal, the at least one opening located above a bottom metallization line and below a top metallization line of the tile.
A die, comprising:
- a plurality of tiles, each tile defining a layer of the die and having a plurality of fixed resource blocks;
- and
- a die seal disposed within an inner boundary of a scribe region surrounding the plurality of tiles, the die seal enabling the plurality of tiles to be coupled to one or more adjacent tiles through interconnect lines routed through an opening defined within a layer of the die seal, the opening located above a bottom metallization line and below a top metallization line of the tile.
A tile comprising:
- a plurality of fixed resource blocks;
- and
- a plurality of logic blocks,
- wherein said tile is configurable to couple to one or more adjacent tiles through interconnect lines routed through a die seal disposed inside a scribe region surrounding the tile and the one or more adjacent tiles, wherein the interconnect lines are configured for facilitating communication between the plurality of fixed resource blocks and the plurality of logic blocks of one or more adjacent tiles, and wherein the tile forms a die layer, the interconnect lines traversing through at least one opening within the die seal, the at least one opening located above a bottom metallization line and below a top metallization line of the tile.
Dependencies are inferred from the claim text.