Fabrication of a vertical heterojunction tunnel-FET
AssigneeInternational Business Machines Corporation
InventorsIsaac Lauer, Amlan Majumdar, Paul M. Solomon, Steven J. Koester
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Abstract
Exemplary embodiments include a method for fabricating a heterojunction tunnel field-effect-transistor (FET), the method including forming a gate region on a silicon layer of a silicon-on-insulator (SOI) substrate, forming a drain region on the silicon layer adjacent the gate region and forming a vertical heterojunction source region adjacent the gate region, wherein the vertical heterojunction source region generates a tunnel path inline with a gate field associated with the gate region.
Claims11
A method for fabricating a heterojunction tunnel field-effect-transistor (FET), the method comprising:
- forming a gate region on a silicon layer of a silicon-on-insulator (SOI) substrate;
- forming a drain region on the silicon layer adjacent the gate region;
- and
- etching an undercut through an oxide layer and between the silicon layer and a silicon substrate layer of the SOI substrate to form a vertical heterojunction source region adjacent the gate region,
- doping the silicon layer and the silicon substrate layer with an n-type dopant,
- wherein the vertical heterojunction source region is configured to define a tunnel path that extends parallel with a height of the gate region and is inline with a gate field associated with the gate region,
- wherein forming the vertical heterojunction source region comprises etching through the silicon layer and an insulating layer of the SOI substrate.
A field effect transistor (FET) device, comprising:
- a silicon-on-insulator (SOI) substrate;
- a gate region disposed on the SOI substrate;
- a drain region adjacent the gate region;
- and
- a vertical heterojunction source region adjacent the gate region, the vertical heterojunction source region being doped with a p-type dopant;
- a first and second semiconductor layer disposed underneath the gate region, an undercut region formed between the first and second semiconductor layers;
- wherein a portion of the source region disposed underneath the gate region is disposed in the undercut region such that the vertical heterojunction source region is configured to define a tunnel path that extends parallel to a height of the gate region and is inline with a gate field associated with the gate region,
- wherein the drain region and the first and second semiconductor layers are n-type.
Dependencies are inferred from the claim text.