Pixel structure, method of manufacturing pixel structure, and active device matrix substrate

A method of manufacturing a pixel structure on a substrate, the pixel structure being driven by a scan line and a data line, the method comprising:

• forming a first patterned metal layer on the substrate, the first patterned metal layer having a common line and a gate;
• forming a first insulation layer, the first insulation layer covering the first patterned metal layer;
• forming a semiconductor pattern on the first insulation layer above the gate;
• forming a second patterned metal layer on the first insulation layer, the second patterned metal layer having a source and a drain, the source and the drain being electrically connected to the semiconductor pattern;
• forming a second insulation layer, the second insulation layer covering the second patterned metal layer and having a contact opening exposing the drain;
• and
• forming an electrode layer on the second insulation layer, the electrode layer having a pixel electrode and a common electrode, the pixel electrode being connected to the drain through the contact opening,
• wherein the common line, the first insulation layer, and the pixel electrode together constitute a first storage capacitor,
• the common line, the drain, and the common electrode together constitute a sandwich structure,
• the common line, the first insulation layer, and the drain together constitute a second storage capacitor,
• the drain, the second insulation layer, and the common electrode together constitute a third storage capacitor, and
• a portion of the drain is extended above the common line and overlapped with the first insulation layer above the common line.

An active device matrix substrate, comprising:

• a substrate;
• and
• a plurality of pixel structures, disposed on the substrate, each of the pixel structures comprising:
• a first patterned metal layer, disposed on the substrate, the first patterned metal layer having a common line and a gate;
• a first insulation layer, covering the first patterned metal layer;
• a semiconductor pattern, located on the first insulation layer above the gate;
• a second patterned metal layer, disposed on the first insulation layer, the second patterned metal layer having a source and a drain, the source and the drain being electrically connected to the semiconductor pattern;
• a second insulation layer, covering the second patterned metal layer, the second insulation layer having a contact opening exposing the drain;
• and
• an electrode layer, disposed on the second insulation layer, the electrode layer having a pixel electrode and a common electrode, the pixel electrode being connected to the drain through the contact opening,
• wherein the common line, the first insulation layer, and the pixel electrode together constitute a first storage capacitor,
• the common line, the drain, and the common electrode together constitute a sandwich structure,
• the common line, the first insulation layer, and the drain together constitute a second storage capacitor,
• the drain, the second insulation layer, and the common electrode together constitute a third storage capacitor, and
• a portion of the drain is extended above the common line and overlapped with the first insulation layer above the common line.

A pixel structure disposed on a substrate and driven by a scan line and a data line, the pixel structure comprising:

• a first patterned metal layer, disposed on the substrate, the first patterned metal layer having a common line and a gate;
• a first insulation layer, covering the first patterned metal layer;
• a semiconductor pattern, located on the first insulation layer above the gate;
• a second patterned metal layer, disposed on the first insulation layer, the second patterned metal layer having a source and a drain, the source and the drain being electrically connected to the semiconductor pattern;
• a first electrode layer, disposed above the second patterned metal layer and electrically connected to the drain;
• a second insulation layer, covering the first electrode layer;
• and
• a second electrode layer, disposed on the second insulation layer,
• wherein the common line, the first insulation layer, and the first electrode layer together constitute a first storage capacitor,
• the first electrode layer, the second insulation layer, and the second electrode layer together constitute a second storage capacitor, and
• a portion of the drain is extended above the common line and overlapped with the first insulation layer above the common line.