Semiconductor device with vertical channel transistor and method for fabricating the same
AssigneeSK hynix Inc.
InventorsHeung-Jae Cho, Tae-Yoon Kim
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Abstract
A method for fabricating a semiconductor device includes forming a plurality of semiconductor body lines in which a plurality of buried bit lines are buried, to be separated by a plurality of trenches, forming a filling layer that fills each of the plurality of trenches, forming a conductive layer over the plurality of semiconductor body lines and the filling layer, forming a plurality of semiconductor pillars over the plurality of semiconductor body lines by etching the conductive layer.
Claims16
A method for fabricating a semiconductor device, comprising:
- forming a plurality of semiconductor body lines in which a plurality of buried bit lines are buried, to be separated by a plurality of trenches;
- forming a filling layer that fills each of the plurality of trenches;
- forming a conductive layer over the plurality of semiconductor body lines and the filling layer;
- and
- forming a plurality of semiconductor pillars over the plurality of semiconductor body lines by etching the conductive layer,
- wherein the filling layer is formed by flowing upper portions of the plurality of semiconductor body lines through a thermal process.
A method for fabricating a semiconductor device, comprising:
- etching a silicon substrate and forming a plurality of silicon body lines that are separated by a plurality of trenches;
- forming a dielectric layer in the trenches to have a height lower than a height of the plurality of silicon body lines;
- forming a filling silicon layer over the dielectric layer through a thermal process that allows silicon migration of the silicon body lines;
- forming a silicon layer over the filling silicon layer and the plurality of silicon body lines;
- and
- forming a plurality of silicon pillars over the plurality of silicon body lines by etching the silicon layer and the filling silicon layer, wherein the plurality of silicon pillars include channel regions of vertical channel transistors.
Dependencies are inferred from the claim text.