Memory access monitoring
AssigneeInternational Business Machines Corporation
InventorsXiaowei Shen, Peter F. Sweeney
Life of this patent
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Abstract
A computer-implemented method for memory access monitoring, implemented by a managed runtime environment computer system including a controller that monitors application behavior and determines actions to be taken to change a behavior of an application, and a runtime, dynamic compiler that analyzes the application and generates code sequences to access a memory access monitoring (MAM) mechanism, includes determining monitor information of a plurality of fields of a memory block to drive an optimization of the application.
Claims11
A non-transitory computer readable storage medium embodying instructions executable by a processor to perform a computer-implemented method of memory access monitoring (MAM), the method comprising the steps of:
- constructing a MAM table comprising a plurality of table entries, wherein each table entry comprises an address register (AR), a control register (CR), and a monitor register (MR);
- identifying a memory block to be monitored, wherein an address of the memory block is specified by setting the AR and a location of the memory block in a memory hierarchy is specified by setting the CR, wherein
- the location is a memory component among a plurality of memory components having different latencies;
- storing, in the MR, monitor information specifying which sub-blocks of the memory block have been accessed and how many times each sub-block has been accessed;
- determining respective latencies for each memory component;
- using one or more hardware performance monitors by counting a number of accesses for each memory component and multiplying the counted number of accesses by a time to access a piece of information, wherein memory latency is calculated in this manner for particular addresses within each memory component;
- reducing the respective latency of the memory block by optimizing the memory block wherein
- an optimization includes field reordering and object splitting each applied according to a size of the memory block,
- wherein applying the optimization comprises:
- recompiling all code that is affected by the optimization;
- and reordering objects whose type has been optimized.
A computer-implemented method for memory access monitoring, implemented by a managed runtime environment computer system comprising
- a controller that monitors application behavior and
- determines an action to be taken to change a behavior of an application, and
- a runtime, dynamic compiler that analyzes the application and generates code sequences to access a memory access monitoring (MAM) mechanism, the computer-implemented method comprises
- determining monitor information of a plurality of fields of a memory block and a location of the memory block in a multi-level memory hierarchy to drive an optimization of the application, wherein
- the monitor information specifies which sub-blocks of the memory block have been accessed and how many times each sub-block has been accessed and
- the location is a memory component among a plurality of memory components having different latencies, and wherein
- the optimization reduces a respective latency of the memory block;
- and wherein
- respective latencies for each memory component are determined using one or more hardware performance monitors by counting a number of accesses for each memory component and multiplying the counted number of accesses by a time to access a piece of information, wherein memory latency is calculated in this manner for particular addresses within each memory component;
- and
- wherein applying the optimization comprises:
- recompiling all code that is affected by the optimization;
- and reordering objects whose type has been optimized.
A non-transitory computer readable storage medium embodying instructions executable by a processor to perform a computer-implemented method of memory access monitoring (MAM), the method comprising the steps of:
- collecting monitor information including a monitored address in a component and a location of the component in a multi-level memory hierarchy;
- wherein
- the multi-level memory hierarchy comprises different components, including the component, wherein
- the different components have different latencies wherein
- respective latencies for each memory component are determined using one or more hardware performance monitors by counting a number of accesses for each memory component and multiplying the counted number of accesses by a time to access a piece of information, wherein memory latency is calculated in this manner for particular addresses within each memory component;
- and
- recording the monitor information for the monitored address, when at least one of, a sub-block of the monitored address is read, a sub-block of the monitored address is modified, and a sub-block of the monitored address is accessed, wherein
- the monitor information for the monitored address in the component in the memory hierarchy is used to drive an optimization reducing a respective latency of the component;
- wherein applying the optimization comprises:
- recompiling all code that is affected by the optimization;
- and reordering objects whose type has been optimized.
Dependencies are inferred from the claim text.