Automatic flow of megacell generation

A system comprising:

• a computer-readable storage medium containing data representing an electronic design, said electronic design comprising a plurality of connected standard cells from a standard library;
• and
• a processor coupled to read the storage medium, the processor configured for:
• generating a timing report for the electronic design, wherein the timing report comprising one or more failed-timing paths and each failed-timing path comprises a plurality of cells;
• generating a megacell for each failed-timing path, wherein:
• the megacell and the failed-timing path perform a same function, and
• generating the megacell for each failed-timing path comprises extracting a set of cascaded logic gates for each failed-timing path;
• determining a critical transistor count for the megacell, wherein the critical transistor count for the megacell includes at least a megacell stack number count;
• determining a critical transistor count for the failed-timing path, wherein the critical transistor count for the failed-timing path includes at least a failed-timing path stack number count;
• determining whether the megacell optimizes the failed-timing path using an optimizing constraint, wherein the optimizing constraint comprises a minimum reduction of the critical transistor count from the failed-timing path to the megacell, and a specified difference in the megacell stack number count and the failed-timing path stack number count;
• replacing the failed-timing path with the megacell when the megacell optimizes the failed-timing path,
• generating a violation-free layout for the megacell using a megacell netlist;
• and,
• incorporating the megacell layout into a layout for the electronic design;
• and,
• an output device coupled to the processor for outputting the layout for the electronic design.

A method of optimizing timing of an electronic design, the method comprising:

• receiving an electronic design comprising a plurality of connected standard cells;
• generating a timing report, using a processor, for the electronic design, wherein the timing report comprises a failed-timing path, the failed-timing path comprises a plurality of cells;
• generating a first megacell for said the failed-timing path, wherein the first megacell and the failed-timing path perform a same function;
• generating a second megacell for a timing path other than the failed-timing path;
• determining a critical transistor count for the failed-timing path;
• determining a critical transistor count for the first megacell;
• determining whether the first megacell optimizes the failed-timing path using a first optimizing constraint comprising a minimum reduction of the critical transistor count from the failed-timing path to the first megacell;
• replacing the failed-timing path with the first megacell when the first megacell optimizes the failed-timing path;
• determining whether the second megacell optimizes the timing path other than the failed-timing path using a second optimizing constraint comprising a specified difference in a second megacell stack number count and a stack number count of the timing path other than the failed-timing path;
• and
• replacing the timing path other than the failed-timing path with the second megacell when the second megacell optimizes the timing path other than the failed-timing path.

A system comprising:

• a computer-readable storage medium containing data representing an electronic design, said electronic design comprising a plurality of connected standard cells from a standard library;
• and
• a processor coupled to read the storage medium, the processor configured for:
• receiving an electronic design comprising a plurality of connected standard cells;
• generating a timing report for the electronic design, wherein the timing report comprises a failed-timing path, the failed-timing path comprises a plurality of cells;
• generating a first megacell for said the failed-timing path, wherein the first megacell and the failed-timing path perform a same function;
• generating a second megacell for a timing path other than the failed-timing path;
• determining a critical transistor count for the failed-timing path;
• determining a critical transistor count for the timing path other than the failed-timing path;
• determining a critical transistor count for the first megacell;
• determining a critical transistor count for the second megacell;
• determining whether the first megacell optimizes the failed-timing path using a first optimizing constraint, wherein the first optimizing constraint comprises:
• a minimum reduction of the critical transistor count from the failed-timing path to the first megacell;
• and
• a specified difference in a first megacell stack number count and a failed-timing path stack number count;
• replacing the failed-timing path with the first megacell when the first megacell optimizes the failed-timing path;
• and
• determining whether the second megacell optimizes the timing path other than the failed-timing path using a second optimizing constraint comprising a minimum reduction of the critical transistor count from the timing path other than the failed-timing path to the second megacell;
• and
• replacing the timing path other than the failed-timing path with the second megacell when the second megacell optimizes the timing path other than the failed-timing path.