System and method for guiding remedial transformations of a circuit design defined by physical implementation data to reduce needed physical corrections for detected timing violations in the circuit design

A system for guiding remedial transformations of a circuit design defined by physical implementation data to reduce needed physical corrections for detected violations in the circuit design, the system comprising:

• a storage memory including physical implementation data for a circuit design including a plurality of timing paths, each path having at least one node thereon;
• a graph-based timing analysis engine coupled to said storage memory, said graph-based timing analysis engine executing to receive and analyze the physical implementation data in operational timing, said graph-based timing analysis engine generating a graph-based datastore in said storage memory identifying a candidate set of defective nodes of the circuit design responsive to detection of an operational timing defect in said circuit design, said graph-based timing analysis engine generating operational timing characteristics including an identification and magnitude of the operational timing defect for each of said candidate set of defective nodes;
• a path-based timing analysis engine coupled to said storage memory and executing on said candidate set of defective nodes to generate a path-based data store in said storage memory identifying operational timing characteristics of said candidate set of defective nodes;
• and,
• a composite timing data store generation module coupled to said storage memory executing to selectively merge operational timing characteristics of said graph-based datastore with operational timing characteristics of said candidate set of defective nodes from said path-based data store to generate a hybrid graph-based and path-based timing data store of said circuit design.