Method and apparatus for implementing a processor interface block with an electronic design automation tool
AssigneeAltera Corporation
InventorSteven Perry
Life of this patent
Estimating the term…
Abstract
An electric design automation (EDA) tool for generating a design of a system on a field programmable gate array (FPGA) includes a library that includes a processor interface block selectable by a designer to represent a component in the design that is assessable to a processor. The EDA tool also includes a processor interface circuitry generation unit to automatically generate circuitry in the design to support the processor interface block without input from the designer.
Claims20
An electric design automation (EDA) tool for generating a design of a system on a target device, comprising:
- a library comprising a processor interface block selectable by a designer to include in the design of the system, wherein the processor interface block is operable to interface with a processor residing off the target device;
- and
- a processor interface circuitry generator operable to automatically generate a circuit design for the processor interface block independent of input from the designer in response to a selection of the processor interface block from the library.
A method for designing a system to be implemented on a target device, comprising:
- providing a library of selectable functional units selectable by a designer to generate a description of the system, wherein the library of selectable functional units comprises a processor interface block accessible by a processor residing off the target device;
- and
- generating a circuit design for the processor interface block in the description of the system, independent of input from the designer, in response to a selection of the processor interface block from the library, wherein at least one of the providing and generating is performed by a computer system.
A non-transitory computer readable medium including a sequence of instructions stored thereon for causing a computer to execute a method comprising:
- providing a library of selectable functional units selectable by a designer to generate a description of a system to be implemented on a target device, wherein the library of selectable functional units comprises a processor interface block;
- and
- generating a circuit design for the processor interface block in the description of the system, independent of input from the designer, in response to a selection of the processor interface block from the library, wherein the circuit design includes a data selector comprising a network of multiplexers.
Dependencies are inferred from the claim text.