Gate array architecture with multiple programmable regions

An integrated circuit comprising:

• a gate array layer comprising a two-dimensional array of logic gates, each logic gate comprising a plurality of transistors, each transistor comprising a plurality of transistor nodes corresponding to different terminals of the transistor;
• at least one upper template-based metal layer coupled to the gate array layer and configured to define at least one of a power distribution network, a clock network and a global signal network, wherein a configuration of traces of the upper template-based metal layer is at least mainly predetermined prior to design of the integrated circuit, at least one lower template-based metal layer coupled to the gate array layer and configured to define an array of tiled cells, wherein a configuration of traces of the at least one lower template-based metal layer is at least mainly predetermined prior to design of the integrated circuit, each of said cells comprising:
• a plurality of staggered horizontal traces each coupled to different transistor nodes such that, for each transistor underlying the cell so as to be interconnected by traces within the cell to form part of a circuit, each transistor node is accessible to allow forming a connection to that transistor node by forming a connection to one of the horizontal traces;
• and
• a plurality of programmable metal layers for interconnecting various ones of said transistors;
• wherein the plurality of programmable metal layers underlies the at least one upper template-based metal layer and comprises at least one programmable metal layer consisting essentially of vertical traces coupled to the staggered horizontal traces.

An integrated circuit comprising:

• a gate array layer comprising a two-dimensional array of logic gates, each logic gate comprising a plurality of transistors, each transistor comprising a plurality of transistor nodes corresponding to different terminals of the transistor;
• at least one upper template-based metal layer coupled to the gate array layer and configured to define at least one of a power distribution network, a clock network and a global signal network, wherein a configuration of traces of the upper template-based metal layer is at least mainly predetermined prior to design of the integrated circuit;
• at least one lower template-based metal layer coupled to the gate array layer and configured to define an array of tiled cells, wherein a configuration of traces of the at least one lower template-based metal layer is at least mainly predetermined prior to design of the integrated circuit, each of said cells comprising:
• a plurality of staggered horizontal traces each coupled to different transistor nodes such that, for each transistor underlying the cell so as to be interconnected by traces within the cell to form part of a circuit, each transistor node is accessible to allow forming a connection to that transistor node by forming a connection to one of the horizontal traces;
• at least one programmable metal layer for interconnecting various ones of said transistors;
• and
• at least one other lower template-based metal layer for interconnecting various ones of said transistors configured to enable transistor-level interconnection between individual ones of said transistors, wherein a configuration of traces of the at least one other lower template-based metal layer is at least mainly predetermined prior to design of the integrated circuit.