US 8,788,983 B2Granted

Method for correcting layout pattern and mask thereof

AssigneeSemiconductor Manufacturing International Corp.

InventorJasmine Zhang

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Abstract

A method for correcting layout pattern and a mask having the corrected layout pattern thereon are provided. In an exemplary method, a first layout pattern including a plurality of first hole patterns can be provided to form an auxiliary pattern in each first hole pattern and to obtain a second layout pattern. The auxiliary pattern can have a dimension smaller than an exposure resolution in a photolithography process. The second layout pattern can then be processed by an optical proximity correction (OPC) to obtain a first modified layout pattern. The first modified layout pattern can include a plurality of modified first hole patterns modified by the OPC. The first modified layout pattern can be simulated to obtain an actual layout pattern such that the actual layout pattern and the first layout pattern have an edge placement error (EPE) within a predetermined range.

Claims20

Dependent claims

A method for correcting a layout pattern, comprising:

providing a first layout pattern, the first layout pattern comprising a first hole pattern for forming a hole in a wafer, wherein the first hole pattern has a cross-sectional shape;
on the first layout pattern, adding an auxiliary pattern in the first hole pattern to form a second layout pattern, the auxiliary pattern having a dimension smaller than an exposure resolution in a photolithography process such that a pattern corresponding to the auxiliary pattern is not formed on the wafer, when a pattern corresponding to the first hole pattern is formed on the wafer;
processing the second layout pattern using an optical proximity correction (OPC) to process the first hole pattern to form a modified first hole pattern but not to process the auxiliary pattern in the second layout pattern to form a first modified layout pattern, the first modified layout pattern comprising the modified first hole pattern by the OPC and the auxiliary pattern non-processed by the OPC;
and
simulating, using a computer, the first modified layout pattern to obtain an actual layout pattern, wherein the actual layout pattern and the first layout pattern have an edge placement error (EPE) within a predetermined range.

2 more elements

Dependencies are inferred from the claim text.

Facts

Application: 13/845,149Filed 18 Mar 2013
Priority: CN 2012 1 011340717 Apr 2012
Published: US 2013/0275928 A117 Oct 2013
Granted: 22 Jul 2014
Term ends: Not estimatedThe source records don’t support an estimate.

Classification8 codes

G06F 30/398
Circuit design at the physical level: design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or…
G03F 1/36
Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles…
G06F 30/00
Computer-aided design [cad]
G06F 2119/18
Details relating to the type or aim of the analysis or the optimisation: manufacturability analysis or optimisation for manufacturability

Family

US 2013/0275928 A1Pre-grant publication · published 17 Oct 2013
US 8,788,983 B2This patent

From the US filing history. Foreign family members aren’t listed.

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