Methods and apparatus to perform error detection and correction

An apparatus to perform error detection and correction, the apparatus comprising:

• a tagged mode selector to dynamically enable a memory controller to operate in a tagged memory mode based on a first setting in a system memory mode register of the memory controller, and to dynamically enable the memory controller to operate in the non-tagged memory mode based on a second setting in a system memory mode register of the memory controller;
• and
• an error correction mode selector to:
• select a fast error correction code process to correct an error when the memory controller detects one error in data or extension bits;
• select a slow error correction code process to correct errors when the memory controller detects two or three errors in the data or the extension bits;
• select a slowest error correction code process to correct errors when the memory controller detects more than three errors in the data or the extension bits;
• and
• select one of a six-error-correction-seven-error-detection per-burst mode or a single-error-correction-dual-error-detection per-transfer mode based on error types in the data when the tagged mode selector enables a non-tagged memory mode in the memory controller.

A non-transitory machine accessible storage medium comprising instructions that, when executed, cause a machine to at least:

• enable a memory controller to operate in one of a tagged memory mode or a non-tagged memory mode;
• when the tagged memory mode is enabled in the memory controller, select a five-error-correction-six-error-detection mode to perform error correction on data or extension bits;
• and
• when the non-tagged memory mode is enabled in the memory controller, select, based on a pattern of previously detected error types in previous data or previous extension bits, one of a six-error-correction-seven-error-detection mode or a single-error-correction-dual-error-detection mode.