Scan chain lockup latch with data input control responsive to scan enable signal

An integrated circuit comprising:

• scan test circuitry;
• and
• additional circuitry subject to testing utilizing the scan test circuitry;
• the scan test circuitry comprising at least one scan chain having a plurality of scan cells;
• the scan test circuitry further comprising at least one lockup latch, the lockup latch being arranged within the scan chain between first and second ones of the scan cells, wherein the lockup latch comprises:
• at least one latching element;
• and
• data input control circuitry configured to control application of data to a data input of the latching element responsive to a scan enable signal;
• wherein the scan chain is controllable between a scan shift mode of operation and a functional mode of operation responsive to the scan enable signal;
• and
• wherein the data input control circuitry is configured to maintain the data input of the latching element at a substantially constant logic value when the
• scan chain is in its functional mode of operation such that switching activity in the latching element is suppressed in said functional mode.

A method comprising:

• configuring a lockup latch between first and second scan cells of a scan chain;
• controlling application of data to a data input of a latching element of the lockup latch responsive to a scan enable signal;
• and
• controlling the scan chain between a scan shift mode of operation and a functional mode of operation responsive to the scan enable signal;
• wherein controlling application of data to the data input of the latching element further comprises maintaining the data input of the latching element at a substantially
• constant logic value when the scan chain is in its functional mode of operation such that switching activity in the latching element is suppressed in said functional mode.

A processing system comprising:

• a processor;
• and
• a memory coupled to the processor and configured to store information characterizing an integrated circuit design;
• wherein the processing system is configured to provide scan test circuitry within the integrated circuit design, the scan test circuitry comprising at least one scan chain having a plurality of scan cells;
• the scan test circuitry further comprising at least one lockup latch, the lockup latch being arranged within the scan chain between first and second ones of the scan cells, wherein the lockup latch comprises:
• at least one latching element;
• and
• data input control circuitry configured to control application of data to a data input of the latching element responsive to a scan enable signal;
• wherein the scan chain is controllable between a scan shift mode of operation and a functional mode of operation responsive to the scan enable signal;
• and
• wherein the data input control circuitry is configured to maintain the data input of the latching element at a substantially constant logic value when the
• scan chain is in its functional mode of operation such that switching activity in the latching element is suppressed in said functional mode.

A scan chain lockup latch comprising:

• at least one latching element;
• and
• data input control circuitry configured to control application of data to a data input of the latching element responsive to a scan enable signal;
• wherein the lockup latch is configured for coupling between first and second scan cells of a scan chain;
• and
• wherein the data input control circuitry comprises logic circuitry having a first input configured to receive the scan enable signal, a second input configured to receive a data signal, and an output coupled to the data input of the latching element.

A scan chain lockup latch comprising:

• at least one latching element;
• and
• data input control circuitry configured to control application of data to a data input of the latching element responsive to a scan enable signal;
• wherein the lockup latch is configured for coupling between first and second scan cells of a scan chain;
• and
• wherein the data input control circuitry comprises a multiplexer having a first selectable input configured to receive a data signal, a second selectable input configured to receive a substantially constant logic value, a control input configured to receive the scan enable signal, and an output coupled to the data input of the latching element.

A scan chain lockup latch comprising:

• at least one latching element;
• and
• data input control circuitry configured to control application of data to a data input of the latching element responsive to a scan enable signal;
• wherein the lockup latch is configured for coupling between first and second scan cells of a scan chain;
• and
• wherein the data input control circuitry comprises an inverter having an input configured to receive the scan enable signal, an output coupled to the data input of the latching element, and upper and lower supply inputs, one of the supply inputs being configured to receive a data signal and the other supply input being coupled to a supply line.