Testing system for integrated circuits including components for receiving clock signals corresponding to different clock domains

An integrated circuit comprising:

• a pin for receiving a test clock signal;
• clock gating cells to direct said test clock signal from said pin towards components included in respective clock domains;
• coupled to each of said gating cells, a dedicated flip-flop for a respective clock domain, said dedicated flip-flop effecting on the cell to which it is coupled a clock gating function during testing of the integrated circuit;
• and
• a logic gate interposed between said dedicated flip-flop and said clock gating cell coupled thereto to effect a gating function based on a scan enable signal by correspondingly managing generation of test patterns for the circuit,
• wherein the output of said logic gate is feedback connected to the D input of said dedicated flip-flop.

A testing method for an integrated circuit comprising:

• receiving a test clock signal on a pin of the integrated circuit;
• providing clock gating cells to direct said test clock signal from said pin towards components included in respective clock domains;
• coupling to each of said gating cells, a dedicated flip-flop for a respective clock domain, said dedicated flip-flop effecting on the cell to which it is coupled a clock gating function during testing of the integrated circuit;
• and
• providing a logic gate interposed between said dedicated flip-flop and said clock gating cell coupled thereto to effect a gating function based on a scan enable signal by correspondingly managing generation of test patterns for the circuit,
• wherein the output of said logic gate is fed back to the D input of said dedicated flip-flop.