Data processing apparatus, trace unit and diagnostic apparatus

A data processing apparatus comprising:

• memory means for storing data, said memory means comprising a plurality of memory locations identified by corresponding memory addresses;
• processing means for performing processing operations in response to instructions;
• and
• trace means for generating a stream of trace data elements indicative of said processing operations performed by said processing means and for outputting said stream of trace data elements;
• wherein:
• said trace means comprises a plurality of reference address register means for storing a plurality of reference addresses;
• and
• said trace means is responsive to said processing means processing an instruction for performing a processing operation associated with an associated memory address to select one of said plurality of reference address register means as a selected reference address register means and to generate and output a trace data element indicating:
• (i) first information indicative of which of said plurality of reference address register means is said selected reference address register means;
• and
• (ii) second information indicative of a difference between said associated memory address and a selected reference address stored in said selected reference address register means;
• and
• wherein said trace means is configured, after generating said trace data element, to perform a reference address updating operation for selectively updating the reference address of at least one of said plurality of reference address register means in dependence on said associated memory address, and
• wherein said reference address updating operation comprises writing said associated memo address to a victim reference address register means of said plurality of reference address registers.

A data processing method for a data processing apparatus comprising a memory comprising a plurality of memory locations identified by corresponding memory addresses, said method comprising the steps of:

• performing processing operations in response to instructions;
• storing a plurality of reference addresses in a plurality of reference address registers;
• generating a stream of trace data elements indicative of said processing operations performed by said processing circuitry;
• and
• outputting said stream of trace data elements;
• wherein:
• said step of generating a stream of trace data elements comprises, in response to performance of a processing operation associated with an associated memory address, selecting one of said plurality of reference address registers as a selected reference address register and generating and outputting a trace data element indicating:
• (i) first information indicative of which of said plurality of reference address registers is said selected reference address register;
• and
• (ii) second information indicative of a difference between said associated memory address and a selected reference address stored in said selected reference address register;
• and
• after generating said trace data element, performing a reference address updating operation for selectively updating the reference address of at least one of said plurality of reference address registers in dependence on said associated memory address, and
• wherein said reference address updating operation comprises writing said associated memory address to a victim reference address register of said plurality of reference address registers.

A trace unit for monitoring processing operations performed by a processing apparatus in response to instructions, said processing apparatus comprising a memory comprising a plurality of memory locations identified by corresponding memory addresses;

• said trace unit comprising:
• trace circuitry configured to generate a stream of trace data elements indicative of said processing operations performed by said processing apparatus and to output said stream of trace data elements;
• wherein:
• said trace circuitry comprises a plurality of reference address registers configured to store a plurality of reference addresses;
• and
• said trace circuitry is responsive to said processing apparatus processing an instruction for performing a processing operation associated with an associated memory address to select one of said plurality of reference address registers as a selected reference address register and to generate and output a trace data element indicating:
• (i) first information indicative of which of said plurality of reference address registers is said selected reference address register;
• and
• (ii) second information indicative of a difference between said associated memory address and a selected reference address stored in said selected reference address register;
• and
• wherein said trace circuitry is configured, after generating said trace data element, to perform a reference address updating operation for selectively updating the reference address of at least one of said plurality of reference address registers in dependence on said associated memory address, and
• wherein said reference address updating operation comprises writing said associated memo address to a victim reference address register of said plurality of reference address registers.

A trace unit for monitoring processing operations performed by a processing apparatus in response to instructions, said processing apparatus comprising a memory means for storing data, said memory means comprising a plurality of memory locations identified by corresponding memory addresses;

• said trace unit comprising:
• trace means for generating a stream of trace data elements indicative of said processing operations performed by said processing apparatus and for outputting said stream of trace data elements;
• wherein:
• said trace means comprises a plurality of reference address register means for storing a plurality of reference addresses;
• and
• said trace means is responsive to said processing apparatus processing an instruction for performing a processing operation associated with an associated memory address to select one of said plurality of reference address register means as a selected reference address register means and to generate and output a trace data element indicating:
• (i) first information indicative of which of said plurality of reference address register means is said selected reference address register means;
• and
• (ii) second information indicative of a difference between said associated memory address and a selected reference address stored in said selected reference address register means;
• said
• wherein said trace means is configured, after generating said trace data element, to perform a reference address updating operation for selectively updating the reference address of at least one of said plurality of reference address register means in dependence on said associated memory address, and
• wherein said reference address updating operation comprises writing said associated memory address to a victim reference address register means of said plurality of reference address registers.

A diagnostic apparatus for analysing a stream of trace data elements indicative of processing operations performed by a processing apparatus in response to instructions, said processing apparatus comprising a memory comprising a plurality of memory locations identified by corresponding memory addresses, said diagnostic apparatus comprising:

• a trace input for receiving said stream of trace data elements;
• and
• diagnostic circuitry configured to analyse said stream of trace data elements to determine a processing outcome of said processing operations;
• wherein:
• said diagnostic circuitry comprises a plurality of reference address registers configured to store a plurality of reference addresses;
• and
• said diagnostic circuitry is responsive to an indication of said processing apparatus processing an instruction for performing a processing operation associated with an associated memory address to:
• (a) locate in said stream of trace data elements a trace data element indicating (i) first information indicative of which of said plurality of reference address registers is a selected reference address register;
• and (ii) second information indicative of a difference between said associated memory address and a selected reference address stored in said selected reference address register;
• and
• (b) determine said associated memory address in dependence on said second information and said selected reference address stored in said selected reference address register;
• wherein said diagnostic circuitry is configured, after determining said associated memory address, to perform a reference address updating operation for selectively updating the reference address of one of said plurality of reference address registers in dependence on said associated memory address;
• and
• wherein said reference address updating operation comprises writing said associated memory address to a victim reference address register of said plurality of reference address registers.

A diagnostic apparatus for analysing a stream of trace data elements indicative of processing operations performed by a processing apparatus in response to instructions, said processing apparatus comprising memory means for storing data, said memory means comprising a plurality of memory locations identified by corresponding memory addresses, said diagnostic apparatus comprising:

• trace input means for receiving said stream of trace data elements;
• and
• diagnostic means for analysing said stream of trace data elements to determine a processing outcome of said processing operations;
• wherein:
• said diagnostic means comprises a plurality of reference address register means for storing a plurality of reference addresses;
• and
• said diagnostic means is responsive to an indication of said processing apparatus processing an instruction for performing a processing operation associated with an associated memory address to:
• (a) locate in said stream of trace data elements a trace data element indicating (i) first information indicative of which of said plurality of reference address register means is a selected reference address register means;
• and (ii) second information indicative of a difference between said associated memory address and a selected reference address stored in said selected reference address register means;
• and
• (b) determine said associated memory address in dependence on said second information and said selected reference address stored in said selected reference address register means;
• wherein said diagnostic means is configured, after determining said associated memory address, to perform a reference address updating operation for selectively updating the reference address of one of said plurality of reference address register means in dependence on said associated memory address;
• and
• wherein said reference address updating operation comprises writing said associated memory address to a victim reference address register means of said plurality of reference address registers.

A method for analysing a stream of trace data elements indicative of processing operations performed by a processing apparatus in response to instructions, said processing apparatus comprising a memory comprising a plurality of memory locations identified by corresponding memory addresses, said method comprising the steps of:

• receiving said stream of trace data elements;
• storing a plurality of reference addresses in a plurality of reference address registers;
• and
• analysing said stream of trace data elements to determine a processing outcome of said processing operations;
• wherein:
• said step of analysing comprises, in response to an indication of said processing apparatus processing an instruction for performing a processing operation associated with an associated memory address:
• (a) locating in said stream of trace data elements a trace data element indicating (i) first information indicative of which of said plurality of reference address registers is a selected reference address register;
• and (ii) second information indicative of a difference between said associated memory address and a selected reference address stored in said selected reference address register;
• and
• (b) determining said associated memory address in dependence on said second information and said selected reference address stored in said selected reference address register;
• and
• after determining said associated memory address, performing a reference address updating operation for selectively updating the reference address of one of said plurality of reference address registers in dependence on said associated memory address;
• and
• wherein said reference address updating operation comprises writing said associated memory address to a victim reference address register of said plurality of reference address registers.