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US 8,788,868 B2Granted
Clock circuits and methods
AssigneeMicron Technology, Inc.
InventorNicholas T. Hendrickson
Life of this patent
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Abstract
Integrated circuits, apparatuses and methods are disclosed, such as a method that includes generating an internal clock signal, receiving an external clock signal, and providing a mixed clock signal at an output. The mixed clock signal has a frequency ranging from a defined maximum frequency of the external clock signal to a frequency margin below a frequency of the internal clock signal. Additional integrated circuits, apparatus and methods are described.
Claims19
An integrated circuit comprising:
- a first input to receive an internal clock signal;
- a second input to receive an external clock signal;
- and
- a comparator coupled to the first input and the second input, the comparator comprising:
- a first plurality of flip-flops coupled to the first input;
- a second plurality of flip-flops coupled to the second input;
- and
- a latch, coupled to an output of the first plurality of flip-flops and an output of the second plurality of flip-flops, that provides either an enable signal for the external clock signal or an enable signal for the internal clock signal in response to the frequency of the external clock signal being less than the frequency of the internal clock signal by less than the frequency margin wherein the frequency margin is determined by a quantity of flip-flops in each of the first and second pluralities of flip-flops.
5 more elements
An apparatus comprising:
- a clock generator circuit in an integrated circuit to generate an internal clock signal;
- an input to receive an external clock signal generated external to the integrated circuit;
- a comparator to compare a frequency of the external clock signal with a frequency of the internal clock signal, the comparator comprising:
- a first plurality of flip-flops coupled to the input;
- a second plurality of flip-flops coupled to the internal clock signal;
- and
- a latch, coupled to an output of the first plurality of flip-flops and an output of the second plurality of flip-flops, that provides an external clock enable signal and an internal clock enable signal;
- and
- a mixed clock circuit coupled to the input and the clock generator circuit to provide at an output one of the internal clock signal or the external clock signal based on the internal clock enable signal and the external clock enable signal, respectively.
6 more elements
A method comprising:
- generating an internal clock signal;
- receiving an external clock signal;
- generating a plurality of enable signals in response to a comparison of the internal clock signal to the external clock signal using a first plurality of flip-flops coupled to the internal clock signal and a second plurality of flip-flops coupled to the external clock signal;
- and
- providing, in response to the plurality of enable signer, a mixed clock signal at an output, the mixed clock signal having a frequency ranging from a defined maximum frequency of the external clock signal to a frequency within a frequency margin of the internal clock signal.
2 more elements
A method comprising:
- generating an internal clock signal;
- receiving an external clock signal;
- providing the internal clock signal to a first plurality of flip-flops;
- providing the external clock signal to a second plurality of flip-flops;
- generating one of a first enable signal or a second enable signal in response to comparing an output of the first plurality of flip-flops with an output of the second plurality of flip-flops;
- operating the integrated circuit according to a mixed clock signal having a frequency that is the frequency of the external clock signal unless the frequency of the external clock signal is more than a frequency margin below the frequency of the internal clock signal;
- and
- operating the integrated circuit according to the mixed clock signal having the frequency of the internal clock signal if the frequency of the mixed clock signal is not to be the frequency of the external clock signal.
5 more elements
Dependencies are inferred from the claim text.