Connected standby sleep state for increased power savings
AssigneeIntel Corporation
InventorJawad Haj-Yihia
Life of this patent
Estimating the term…
Abstract
Power consumption and dissipation during sleep states of processors is reduced using a novel connected standby sleep state. In the connected standby sleep state a dedicated power plane is used to maintain processor context. To conserve power, unnecessary components on the processor are powered down, including all of the clock components, and wakeup sources previously directed to the processor are directed to a platform control hub. The platform control hub sustains certain architectural functions for the processor during connected standby sleep state, and manages the wakeup logic for returning the processor to the preceding sleep state.
Claims20
A system comprising:
- a processor including a plurality of processing cores, a cache memory, and an integrated voltage regulator to be a dedicated power plane to enable the cache memory to store a context of the processor when the processor is in a connected standby sleep state;
- a platform control hub coupled to the processor;
- an external voltage regulator;
- and
- an embedded controller;
- wherein the processor is to enter the connected standby sleep state from a deep sleep state upon:
- powering of the cache memory with the dedicated power plane, the dedicated power plane separate from a sustain power plane that powers the cache memory in the deep sleep state;
- powering down of remaining components powered by the sustain power plane and powering down of the sustain power plane;
- redirection of wakeup sources for handling processor wakeup and context restore to the platform control hub;
- and
- transference of at least one architectural function from the processor to the platform control hub.
A non-transitory machine-readable storage medium having stored thereon instructions, which if performed by a machine cause the machine to perform a method comprising:
- transferring power delivery to a cache memory storing a context of a processor in a deep sleep state from a sustain power plane to a dedicated power plane of the processor, wherein the dedicated power plane is active and the sustain power plane is inactive in a connected standby sleep state;
- redirecting wakeup sources for the processor to a platform control hub;
- powering down the sustain power plane;
- gating a reference clock operating in the processor;
- entering the connected standby sleep state;
- and
- awaiting an arrival of a wakeup source for the processor in the platform control hub while in the connected standby sleep state.
A processor comprising:
- at least one processing core;
- a cache memory to store a context of the processor in a deep sleep state;
- and
- a wake logic to handle a wake event for the processor, wherein after entry into the deep sleep state, the processor is to:
- transfer the cache memory to be powered from a dedicated power plane of the processor instead of a sustain power plane of the processor;
- redirect wakeup sources for the processor to a platform control hub coupled to the processor;
- and
- power down the sustain power plane, and gate a reference clock to enable the platform control hub to await an arrival of at least one redirected wakeup source, to enable the processor to enter a connected standby sleep state.
Dependencies are inferred from the claim text.