Programmable atomic memory using stored atomic procedures

A method comprising:

• a processing core in a multi-processing core system validating that a sequence of instructions meets a set of one or more atomicity criteria to produce a validated sequence of instructions configured to access data from one or more cache lines via one or more target registers, wherein the one or more atomicity criteria include a criterion that no instruction in the specified sequence instructs the processing core to access data from memory that is shared with one or more other processing cores other than via the one or more target registers;
• the processing core storing the validated sequence of instructions such that the stored validated sequence of instructions is executable as an atomic memory transaction without further validation for atomicity;
• and
• executing, after the storing, the validated sequence as an atomic memory transaction, wherein executing the validated sequence of instructions as an atomic memory transaction includes storing data from the one or more cache lines in the one or more target registers.

A non-transitory computer readable storage medium comprising a data structure which is operated upon by a program executable on a computer system, the program operating on the data structure to perform a portion of a process to fabricate an integrated circuit including circuitry described by the data structure, the circuitry described in the data structure including:

• a processing core in a multi-processing core system, the processing core being configured to:
• validate that a specified sequence of instructions meets a set of one or more atomicity criteria to produce a validated sequence of instructions configured to access data from one or more cache lines via one or more target registers, wherein the one or more atomicity criteria include a criterion that no instruction in the specified sequence instructs the processing core to access data from shared memory other than via the one or more target registers;
• store the validated sequence of instructions such that the stored validated sequence of instructions is executable as an atomic memory transaction without requiring re-validation;
• and
• access the stored validated sequence of instructions for execution as an atomic transaction, wherein execution of the validated sequence of instructions as an atomic memory transaction includes storing data from the one or more cache lines in the one or more target registers.