US 8,788,792 B2 · Apparatus for executing programs for a first computer architecture on a computer of a second architecture

Abstract

A multi-instruction set architecture (ISA) computer system includes a computer program, a first processor, a second processor, a profiler, and a translator. The computer program includes instructions of a first ISA, the first ISA having a first complexity. The first processor is configured to execute instructions of the first ISA. The second processor is configured to execute instructions of a second ISA, the second ISA being different than the first ISA and having a second complexity, wherein the second complexity is less than the first complexity. The profiler is configured to select a block of the computer program for translation to instructions of the second ISA, wherein the block includes one or more instructions of the first ISA. The translator is configured to translate the block of the first ISA into instructions of the second ISA for execution by the second processor.

Claims20

Dependent claims

A multi-instruction set architecture (ISA) computer system, comprising:

a computer program including instructions of a first ISA, the first ISA having a first complexity;
a first processor configured to execute instructions of the first ISA;
a second processor configured to execute instructions of a second ISA, the second ISA being different than the first ISA and having a second complexity, wherein the second complexity is less than the first complexity;
wherein the ISA is indicated in the computer program by one bit in each page of instructions in the computer program;
a profiler configured to select a block of the computer program for translation to instructions of the second ISA, wherein the block includes one or more instructions of the first ISA;
and
a translator configured to translate the block of the first ISA into instructions of the second ISA for execution by the second processor.

4 more elements

Dependencies are inferred from the claim text.

Facts

Application

13/371,766Filed 13 Feb 2012 · continuation

Priority

28 Jan 1999

Published

US 2012/0144167 A17 Jun 2012

Granted

22 Jul 2014

Term ends

Not estimatedThe source records don’t support an estimate.

Classification5 codes

G06F 9/45554
Hypervisors; Virtual machine monitors: instruction set architectures of guest OS and hypervisor or native processor differ, e.g. Bochs or…
G06F 9/30174
Runtime instruction translation, e.g. macros: for non-native instruction set, e.g. Javabyte, legacy code
G06F 9/30189
Instruction operation extension or modification: according to execution mode, e.g. mode flag
G06F 9/3861
Concurrent instruction execution, e.g. pipeline or look ahead: recovery, e.g. branch miss-prediction, exception handling

Family

Application09/239,194Parent of this continuation-in-part · filed 28 Jan 1999

Application60/176,610Us provisional application · filed 18 Jan 2000

PCT/US00/02239Parent of this continuation-in-part · filed 28 Jan 2000

Application09/626,325Parent of this continuation · filed 26 Jul 2000

Application09/672,424Parent of this continuation-in-part · filed 28 Sep 2000

US 7,065,633 B1Parent of this continuation · filed 20 Jun 2006

Application11/904,007Parent of this continuation · filed 25 Sep 2007

US 7,275,246 B1Parent of this continuation-in-part · filed 25 Sep 2007

US 8,127,121 B2Parent of this continuation · filed 28 Feb 2012

US 2012/0144167 A1Pre-grant publication · published 7 Jun 2012

Application11/904,007Parent of this continuation-in-part

Application09/672,424Parent of this continuation

Application09/626,325Parent of this continuation-in-part

US 2008/0216073 A1Published application

US 8,788,792 B2This patent

From the US filing history. Foreign family members aren’t listed.

Apparatus for executing programs for a first computer architecture on a computer of a second architecture

Life of this patent

Apparatus for executing programs for a first computer architecture on a computer of a second architecture

Life of this patent

Abstract

Claims20