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US 8,788,790 B2Granted
Maintaining processor resources during architectural events
AssigneeIntel Corporation
InventorsJason W Brandt, Sanjoy K Mondal, Richard A Uhlig, Gilbert Neiger, Robert T George
Life of this patent
Estimating the term…
Abstract
In one embodiment of the present invention, a method includes switching between a first address space and a second address space, determining if the second address space exists in a list of address spaces; and maintaining entries of the first address space in a translation buffer after the switching. In such manner, overhead associated with such a context switch may be reduced.
Claims5
A processor, comprising:
- an execution logic to support a virtual machine monitor (VMM) to provide an abstraction of one or more virtual machines (VMs) to a plurality of guests running on the one or more VMs, each of the plurality of guests to include an operating system (OS) and software, the VMM to provide access to each of the one or more VMs to a set of physical resources including processor resources, memory, and input/output (IO) devices,
- a translation lookaside buffer (TLB) having a plurality of page table entries (PTEs) to translate virtual addresses to physical addresses of memory pages, each PTE including:
- an address space identifier (ASID) to identify an address space associated with the PTE;
- a thread identifier (ID) to identify a thread associated with the PTE,
- a valid bit;
- and
- a current ASID register to store a current ASID that is to be updated to switch to a different address space,
- wherein the execution logic, in response to a context switch, based on ASIDs of the PTEs and the current ASID stored in the current register, is to either not invalidate any PTEs of the TLB or to selectively invalidate one or more PTEs of the TLB.
5 more elements
A system comprising:
- a processor comprising:
- an execution logic to support a virtual machine monitor (VMM) to provide an abstraction of one or more virtual machines (VMs) to a plurality of guests running on the one or more VMs, each of the plurality of guests to include an operating system (OS) and software, the VMM to provide access to each of the one or more VMs to a set of physical resources including processor resources, memory, and input/output (IO) devices,
- a translation lookaside buffer (TLB) having a plurality of page table entries (PTEs) to translate virtual addresses to physical addresses of memory pages, each PTE including:
- an address space identifier (ASID) to identify an address space associated with the PTE,
- a thread identifier (ID) to identify a thread associated with the PTE,
- a valid bit;
- and
- a current ASID register to store a current ASID that is to be updated to switch to a different address space, wherein the execution logic, in response to a context switch, based on ASIDs of the PTEs and the current ASID stored in the current register, is to either not invalidate any PTEs of the TLB or to selectively invalidate one or more PTEs of the TLB;
- and
- a dynamic random access memory coupled to the processor.
7 more elements
Dependencies are inferred from the claim text.