Power filter in data translation look-aside buffer based on an input linear address
AssigneeAdvanced Micro Devices, Inc.
InventorsDeepika Kapil, David Hugh McIntyre
Life of this patent
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Abstract
A method and an apparatus for power filtering in a Translation Look-aside Buffer (TLB) are described. In the method and apparatus, power consumption reduction is achieved by suppressing physical address (PA) reads from random access memory (RAM) if the previously translated linear address (LA), or virtual address (VA), is the same as the currently requested LA. To provide the correct translation, the output of the TLB is maintained if the previously translated LA and the LA currently requested for translation are the same.
Claims17
A method for reducing power consumption in memory address translation, the method comprising:
- maintaining a physical address (PA) corresponding to a previously translated linear address (LA) as an output if the previously translated LA is the same as a received LA;
- and suppressing reading of a PA corresponding to the received LA if the previously translated LA is the same as the received LA, wherein a reset clock signal is suppressed to maintain the PA.
A memory address translation device comprising:
- circuitry configured to maintain a physical address (PA) corresponding to a previously translated linear address (LA) as an output if the previously translated LA is the same as a received LA:
- and
- circuitry configured to suppress reading of a PA corresponding to the received LA if the previously translated LA is the same as the received LA,
- wherein a reset clock signal is suppressed to maintain the PA.
A computer system comprising:
- a processor including circuitry configured to maintain a physical address (PA) corresponding to a previously translated linear address (LA) as an output if the previously translated LA is the same as a received LAI and
- circuitry configured to suppress reading of a PA corresponding to the received LA if the previously translated LA is the same as the received LA,
- wherein a reset clock signal is suppressed to maintain the PA.
A non-transitory computer-readable storage medium storing a set of instructions for execution by one or more processors to reduce power consumption in a Translation Look-aside Buffer (TLB), the set of instructions comprising:
- a maintaining code segment for maintaining a physical address (PA) corresponding to a previously translated linear address (LA) as an output if the previously translated LA is the same as a received LA;
- and
- a suppressing code segment for suppressing reading of a PA corresponding to the received LA if the previously translated LA is the same as the received LA,
- wherein a reset clock signal is suppressed to maintain the PA.
Dependencies are inferred from the claim text.