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US 8,788,780 B2Granted
Signal restoration circuit, latency adjustment circuit, memory controller, processor, computer, signal restoration method, and latency adjustment method
AssigneeFujitsu Limited
InventorsNoriyuki Tokuhiro, Noriyuki Takahashi, Shinya Aiso
Life of this patent
Estimating the term…
Abstract
A signal restoration circuit includes a storage configured to store input signals by disposing the input signals in an input order, the input signals being readable from the storage in the disposed order, and a storage controller configured to control delay time from an input of the input signal to an output in the storage based on delay information of the input signal.
Claims19
A signal restoration circuit comprising:
- a storage configured to store input signals by disposing the input signals in an input order, the input signals being readable from the storage in the disposed order;
- and
- a storage controller configured to control delay time from an input of the input signals to an output in the storage based on delay information,
- wherein the delay information is attached to each of the input signals and quantitatively represents a delay clock time of each of the input signals.
1 more element
A signal restoration method comprising:
- storing input signals in a storage by disposing the input signals in an input order, the stored input signals being readable from the storage in the disposed order;
- and
- controlling a delay time from an input of the input signals to an output in the storage based on delay information,
- wherein the delay information is attached to each of the input signals and quantitatively represents a delay clock time of each of the input signals.
1 more element
Dependencies are inferred from the claim text.