System and method for explicitly managing cache coherence
AssigneeNVIDIA Corporation
InventorWilliam James Dally
Life of this patent
Estimating the term…
Abstract
One embodiment of the present invention sets forth am extension to a cache coherence protocol with two explicit control states, P (private), and R (read-only), that provide explicit program control of cache lines for which the program logic can guarantee correct behavior. In the private state, only the owner of a cache line can access the cache line for read or write operations. In the read-only state, only read operations can be performed on the cache line, thereby disallowing write operations to be performed.
Claims18
A method for implementing cache coherency across a plurality of cache units coupled to a random access memory unit, the method comprising:
- receiving a request for setting a state corresponding to one or more cache lines in a set of cache lines to an explicit control state;
- transmitting a message to a global directory associated with the plurality of cache units, the message requesting a transition to the explicit control state;
- and
- upon receiving a reply from the global directory, setting the state corresponding to the one or more cache lines to the explicit control state, wherein, when the state corresponding to a first cache line in the one or more cache lines is set to an explicit control state, only a pre-determined set of memory access operations can be performed on the first cache line and any memory access operations performed on the first cache line are not tracked by the global directory.
A cache controller for implementing cache coherency across a plurality of cache units coupled to a direct random access memory unit, the cache controller configured to:
- receive a request for setting a state corresponding to one or more cache lines in a set of cache lines to an explicit control state;
- transmitting a message to a global directory associated with the plurality of cache units, the message requesting a transition to the explicit control state;
- and
- upon receiving a reply from the global directory, set the state corresponding to every cache line included in the one or more cache lines to the explicit control state, wherein, when the state corresponding to a first cache line in the one or more cache lines is set to an explicit control state, only a pre-determined set of memory access operations can be performed on the first cache line and any memory access operations performed on the first cache line are not tracked by the global directory.
A computer system, comprising:
- a plurality of processing engines, each coupled to a different cache unit in a plurality of cache units;
- an off-chip memory coupled to the plurality of cache units;
- and
- a cache controller configured to implement cache coherency across the plurality of cache units, the cache controller configured to:
- receive a request for setting a state corresponding to one or more cache lines in a set of cache lines to an explicit control state;
- transmit a message to a global directory associated with the plurality of cache units, the message requesting a transition to the explicit control state;
- and
- upon receiving a reply from the global directory, set the state corresponding to every cache line included in the one or more cache lines to the explicit control state, wherein, when the state corresponding to a first cache line in the one or more cache lines is set to an explicit control state, only a pre-determined set of memory access operations can be performed on the first cache line and any memory access operations performed on the first cache line are not tracked by the global directory.
Dependencies are inferred from the claim text.