Implementing memory interface with configurable bandwidth
AssigneeInternational Business Machines Corporation
InventorsGerald K. Bartley, John M. Borkenhagen, Philip R. Germann
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Abstract
A method and system are provided for implementing enhanced memory performance management with configurable bandwidth versus power usage in a chip stack of memory chips. A chip stack of memory chips is connected in a predefined density to allow a predefined high bandwidth connection between each chip in the stack, such as with through silicon via (TSV) interconnections. Large-bandwidth data transfers are enabled from the memory chip stack by trading off increased power usage for memory performance on a temporary basis.
Claims17
A method for implementing enhanced memory performance management comprising:
- providing at least one memory chip stack having a predefined connection density to enable a predefined high bandwidth connection between each chip in said memory chip stack;
- and
- providing said at least one memory chip stack with a memory controller and a plurality of chip rank levels in said memory chip stack including at least a chip rank level one adjacent said controller;
- a chip rank level two above said chip rank level one;
- and a chip level three above said chip rank level two;
- providing a normal bandwidth configuration for said at least one memory chip stack with said chip rank level one with a first bandwidth for data;
- said chip rank level two with a second bandwidth for data and said chip rank level three with a third bandwidth for data;
- said first bandwidth greater than both said second bandwidth and said third bandwidth;
- selectively enabling a high bandwidth data transfer from said memory chip stack on a temporary basis;
- said high bandwidth data transfer including an equal bandwidth for said first bandwidth, said second bandwidth and said third bandwidth.
A system for implementing memory performance management in a computer system comprising:
- a memory including at least one memory chip stack having a predefined connection density to enable a predefined high bandwidth connection between each chip in said memory chip stack;
- a memory controller coupled to said at least one memory chip stack;
- and said memory chip stack including a plurality of chip rank levels with a chip rank level one adjacent said controller;
- a chip rank level two above said chip rank level one;
- and a chip level three above said chip rank level two;
- a data transfer bandwidth control;
- said memory controller, responsive to said data transfer bandwidth control, providing a normal bandwidth configuration for said at least one memory chip stack including said chip rank level one with a first bandwidth for data;
- said chip rank level two with a second bandwidth for data and said chip rank level three with a third bandwidth for data;
- said first bandwidth greater than both said second bandwidth and said third bandwidth;
- said memory controller, responsive to said data transfer bandwidth control, selectively enabling a high bandwidth data transfer from said memory chip stack on a temporary basis;
- said high bandwidth data transfer including an equal bandwidth for said first bandwidth, said second bandwidth and said third bandwidth.
Dependencies are inferred from the claim text.