Multilevel memory bus system for solid-state mass storage

A multilevel memory bus system for a solid-state storage device that includes a plurality of semiconductor memory devices, a host interface, at least one flash-specific-DMA controller, and a local processing system that includes a local memory, the multilevel memory bus system comprising:

• an intermediate bus disposed to couple to said at least one flash-specific DMA controller;
• a first flash memory bus disposed to couple to at least one semiconductor memory device from the plurality of semiconductor memory devices, said at least one semiconductor memory device including a first semiconductor memory device;
• a first flash buffer circuit coupled to said intermediate bus and to said first flash memory bus;
• and wherein said intermediate bus is disposed to transfer data at a first data path transfer rate, said first flash memory bus is disposed to transfer data at a second data path transfer rate, and said first and second data path transfer rates are different and said first data path transfer rate higher than said second data path transfer rate;
• a first output that provides a first data path clock signal having a first clock frequency;
• a second output that provides a second data path clock signal having a second clock frequency;
• and said first clock frequency is at least equal to said second clock frequency;
• said intermediate bus includes a first data path having a first bus width;
• said first flash buffer circuit includes a first intermediate bus interface having an interface data throughput that is proportional to said first bus width, said first clock frequency, and a selected sampling rate;
• a strobe output disposed to provide a first strobe signal having a first strobe frequency;
• wherein said selected sampling rate is at least twice as that of said first strobe frequency;
• wherein said intermediate bus interface has an interface data throughput that is defined by:
• IBthru=DataWidth IB*FREQfactor*FREQ*DS where said IBthru is equal to said interface data throughput, said DataWidth IB is equal to said first bus width, said FREQfactor is equal to the quotient of said first frequency divided by said second clock frequency rounded to the nearest integer, said FREQ is equal to said second clock frequency, and said DS is equal to said selected integer multiple.