Large multiplier for programmable logic device
AssigneeAltera Corporation
InventorsMartin Langhammer, Kumara Tharmalingam
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Abstract
A plurality of specialized processing blocks in a programmable logic device, including multipliers and circuitry for adding results of those multipliers, can be configured as a larger multiplier by adding to the specialized processing blocks selectable circuitry for shifting multiplier results before adding. In one embodiment, this allows all but the final addition to take place in specialized processing blocks, with the final addition occurring in programmable logic. In another embodiment, additional compression and adding circuitry allows even the final addition to occur in the specialized processing blocks.
Claims20
For use in an integrated circuit having a plurality of specialized processing blocks, each of said specialized processing blocks having a plurality of multipliers of a first size arranged in units of a first number of multipliers, a method of performing a multiplication operation of a second size larger than said first size, said method comprising:
- decomposing said multiplication operation of said second size into a plurality of multiplication operations of different sizes, each of said different sizes being smaller than said second size;
- performing a multiplication operation of a first one of said different sizes using said first number of multipliers in a first one of said units;
- performing a multiplication operation of a second one of said different sizes smaller than said first one of said different sizes using one of said multipliers in a second one of said units;
- performing a plurality of multiplication operations of a third one of said different sizes, smaller than said first one of said different sizes and larger than said second one of said different sizes, using, for each respective one of said multiplication operations of said third one of said different sizes, a respective subset of said multipliers in a third one of said units;
- aligning outputs of said plurality of multiplication operations of said third one of said different sizes for addition within said third one of said units, to form a result of said multiplication operations of said third one of said different sizes;
- and
- adding results of said multiplication operations of said first, second and third ones of said different sizes.
An integrated circuit having a plurality of specialized processing blocks, each of said specialized processing blocks having a plurality of multipliers of a first size arranged in units of a first number of multipliers, wherein:
- said integrated circuit is configured to perform a multiplication operation of a second size larger than said first size by decomposition of said multiplication operation of said second size into a plurality of multiplication operations of different sizes, each of said different sizes being smaller than said second size;
- and
- said integrated circuit comprises:
- said first number of multipliers in a first one of said units configured to perform a multiplication operation of a first one of said different sizes,
- one of said multipliers in a second of one said units configured to perform a multiplication operation of a second one of said different sizes smaller than said first one of said different sizes;
- a plurality of respective subsets of said multipliers in a third one of said units configured to perform a plurality of respective multiplication operations of a third one of said different sizes, smaller than said first one of said different sizes and larger than said second one of said different sizes;
- a shifter configured to align outputs of said plurality of multiplication operations of a third one of said different sizes for addition within said third one of said units, to form a result of said multiplication operations of said third one of said different sizes;
- and
- circuitry configured to add results of said multiplication operations of said first, second and third ones of said different sizes.
A non-transitory data storage medium encoded with non-transitory machine-executable instructions for performing a method of programmably configuring an integrated circuit to perform a multiplication operation of a second size larger than said first size by decomposition of said multiplication operation of said second size into a plurality of multiplication operations of different sizes, each of said different sizes being smaller than said second size, wherein said integrated circuit has a plurality of specialized processing blocks, each of said specialized processing blocks having a plurality of multipliers of a first size arranged in units of a first number of multipliers, said instructions comprising:
- instructions for configuring said first number of multipliers in a first one of said units to perform a multiplication operation of a first one of said different sizes;
- instructions for configuring one of said multipliers in a second of one said units to perform a multiplication operation of a second one of said different sizes smaller than said first one of said different sizes;
- instructions for configuring a plurality of respective subsets of said multipliers in a third one of said units configured to perform a plurality of respective multiplication operations of a third one of said different sizes, smaller than said first one of said different sizes and larger than said second one of said different sizes;
- instructions for configuring a shifter to align outputs of said plurality of multiplication operations of a third one of said different sizes for addition within said third one of said units, to form a result of said multiplication operations of said third one of said different sizes;
- and
- instructions for configuring circuitry to add results of said multiplication operations of said first, second and third ones of said different sizes.
Dependencies are inferred from the claim text.