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US 8,788,553 B1Granted
Method and circuit for providing digital frequency synthesis
AssigneeXilinx, Inc.
InventorsTed Lee, Alireza S. Kaviani
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Abstract
An integrated circuit for providing digital frequency synthesis is disclosed. For example, the integrated circuit comprises a phase detector for receiving a reference clock signal and an oscillator clock signal, wherein the phase detector outputs an error signal. The integrated circuit further comprises a synthesizer control block, coupled to the phase detector, for receiving the error signal to generate a delay select signal, wherein the synthesizer control block comprises an integral adjustment filter and a proportional adjustment filter.
Claims16
An integrated circuit, comprising:
- a phase detector for receiving a reference clock signal and an oscillator clock signal, wherein said phase detector outputs an error signal;
- and
- a synthesizer control block, coupled to said phase detector, for receiving said error signal to generate a delay select signal, wherein said synthesizer control block comprises an integral adjustment filter and a proportional adjustment filter, wherein said synthesizer control block further comprises a phase deviation filter, wherein said phase deviation filter is coupled to said integral adjustment filter and said proportional adjustment filter, and wherein said integral adjustment filter and said proportional adjustment filter are configured to provide respective outputs for generating said delay select signal that controls an amount of delay to be applied to said oscillator clock signal;
- wherein said phase deviation filter employs a counter for counting a number of concurrences of said reference clock signal and said oscillator clock signal to determine whether an overflow condition or an underflow condition exists.
1 more element
An integrated circuit, comprising:
- a phase detector for receiving a reference clock signal and an oscillator clock signal, wherein said phase detector outputs an error signal;
- and
- a synthesizer control block, coupled to said phase detector, for receiving said error signal to generate a delay select signal, wherein said synthesizer control block comprises:
- an integral adjustment filter;
- a proportional adjustment filter, wherein said error signal is provided to said integral adjustment filter and said proportional adjustment filter, and wherein said integral adjustment filter and said proportional adjustment filter are configured to provide respective outputs for generating said delay select signal that controls an amount of delay to be applied to said oscillator clock signal;
- a fractional counter coupled to said integral adjustment filter;
- a first signal generator;
- and
- a second signal generator;
- wherein the first and second signal generators are coupled to receive respective outputs from the fractional counter, and wherein the second signal generator is coupled to receive the output from the proportional adjustment filter.
7 more elements
An integrated circuit, comprising:
- a phase detector for receiving a reference clock signal and an oscillator clock signal, wherein said phase detector outputs an error signal;
- a synthesizer control block, coupled to said phase detector, for receiving said error signal to generate a delay select signal, wherein said synthesizer control block comprises:
- an integral adjustment filter;
- a proportional adjustment filter, wherein said error signal is provided to said integral adjustment filter and said proportional adjustment filter, and wherein said integral adjustment filter and said proportional adjustment filter are configured to provide respective outputs for generating said delay select signal that controls an amount of delay to be applied to said oscillator clock signal;
- a spread adjustment filter;
- a fractional counter coupled to said integral adjustment filter and said spread adjustment filter;
- a first signal generator;
- and
- a second signal generator;
- wherein the first and second signal generators are coupled to receive respective outputs from the fractional counter, and wherein the second signal generator is coupled to receive the output from the proportional adjustment filter.
7 more elements
Dependencies are inferred from the claim text.