Delay analysis processing of semiconductor integrated circuit

A delay analysis method for analyzing a delay property of a chip with reference to a cell timing library, said delay analysis method comprising:

• distributing at least one clock path toward an entire surface of the chip including an internal area of a macro based on a top netlist input thereto, thus producing a global clock distribution-implemented top netlist and global clock layout data;
• inputting the global clock distribution-implemented top netlist and outputting a regional netlist of a region of a chip;
• receiving the regional netlist to perform a layout process and outputting a layout-completed regional netlist and regional layout data;
• performing, by a processor, RC simulation to calculate a delay time with respect to a specific region of the chip based on the cell timing library, the regional layout data and the layout-completed regional netlist, representing the specific region of the chip associated to the global clock distribution-implemented top netlist, thus producing regional delay information;
• annotating a clock path by the global clock path delay information including edge information input thereto with respect to an initial stage of the specific region of the chip, thus producing a global clock delay-annotated regional netlist;
• producing a regional delay-annotated netlist based on the global clock delay-annotated regional netlist including the clock path annotated by global clock path delay information including the edge information input thereto with respect to the initial stage of the specific region of the chip and the regional delay information;
• inputting timing constraint information in connection with the regional delay-annotated regional netlist to calculate a delay time of signal path, a delay time of the clock path, and a clock skew;
• and
• checking whether or not a relationship between the delay time of the signal path and the delay time of the clock path meets the timing constraint information, thus producing delay analysis information.

A non-transitory storage medium storing a delay analysis program, executable by a computer, to implement a delay analysis method for analyzing a delay property of a chip, said delay analysis method comprising:

• distributing at least one clock path toward an entire surface of the chip including an internal area of a macro based on a top netlist input thereto, thus producing a global clock distribution-implemented top netlist and global clock layout data inputting the global clock distribution-implemented top netlist and outputting a regional netlist of a region of a chip
• receiving the regional netlist to perform a layout process and outputting a layout-completed regional netlist and regional layout data;
• performing RC simulation to calculate a delay time with respect to a specific region of the chip based on the cell timing library, the regional layout data and the layout completed regional netlist, representing the specific region of the chip associated to the global clock distribution-implemented top netlist, thus producing regional delay information;
• annotating a clock path by global clock delay information including edge information input thereto with respect to an initial stage of the specific region of the chip thus producing a global clock delay-annotated regional netlist;
• producing a regional delay-annotated netlist based on the global clock delay annotated regional netlist including the clock path annotated by global clock pat delay information including the edge information input thereto with respect to the initial stage of the specific region of the chip and the regional delay information;
• inputting timing constraint information in connection with the regional delay-annotated regional netlist to calculate a delay time of a signal path, a delay time of the clock path, and a clock skew;
• and
• checking whether or not a relationship between the delay time of the signal path and the delay time of the clock path meets the timing constraint information, thus producing delay analysis information.