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US 8,787,464 B1Granted
Hadamard transformation of data for video compression
AssigneeNVIDIA Corporation
InventorsPankaj Chaurasia, Shankar Moni
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Abstract
A video processor is described, which is useful for implementing a Hadamard transform process, in compliance with the H.264 standard. The video processor includes an input, for receiving a block of image data. The image data is loaded into an internal register. In response to receiving a SIMD instruction, a multiplier, which incorporates the H.264 Hadamard transform matrix in its associated hardware, processes the block of image data, and writes the resulting partially transformed pixel data back to the internal register, transposing the data during the process.
Claims20
A video processor comprising:
- an input for receiving a Direct-Current (DC) block, said DC block comprising a plurality of DC values;
- an internal register for storing said plurality of DC values;
- a multiplier, comprising a Hadamard transform matrix and configured to receive Single Instruction Multiple Data (SIMD) instructions, wherein upon receiving a first transform SIMD instruction, said multiplier operable to perform a 1-D Hadamard transform of said plurality of DC values using said Hadamard transform matrix, operable to produce a partially transformed plurality of DC values, and further operable to write said partially transformed plurality of DC values directly in a transposed manner to said internal register as transposed plurality of DC values to save processor cycles;
- and
- wherein upon receiving a second transform SIMD instruction, said multiplier is operable to perform a 1-D Hadamard transform of said transposed plurality of DC values using said Hadamard transform matrix, producing a Hadamard transformed plurality of DC values, and is operable to write said Hadamard transformed plurality of DC values directly in a transposed manner to said internal register to save processor cycles.
2 more elements
A method comprising:
- loading a plurality of pixel data corresponding to a block of image data into a single register;
- in response to receiving a first Hadamard transform Single Instruction Multiple Data (SIMD) instruction from a software controller, processing said plurality of pixel data in a hardware processor, said processing comprising multiplying said plurality of pixel data by a hardware-implemented Hadamard transform matrix to produce a plurality of transformed pixel data and writing said plurality of transformed pixel data directly in a transposed form into said single register as a plurality of transposed intermediary data to save processor cycles;
- and
- in response to receiving a second Hadamard transform Single Instruction Multiple Data (SIMD) instruction from a software controller, further processing said plurality of transposed intermediary data in said hardware processor by multiplying said plurality of transposed intermediary data by said Hadamard transform matrix to produce a result and writing the result directly in a transposed form into said single register as a plurality of Hadamard transformed data to save processor cycles.
1 more element
A computing system comprising:
- a bus;
- a processor coupled to said bus;
- a memory coupled to said bus;
- and
- a video processor coupled to said bus, said video processor comprising:
- an input for receiving a block of image data, said image data comprising a plurality of pixel data;
- an internal register for storing said plurality of pixel data;
- a multiplier, comprising a transform matrix and configured to receive Single Instruction Multiple Data (SIMD) instructions from a software control structure, wherein upon receiving a Hadamard transform SIMD instruction, said multiplier is operable to perform a 1-D transform of said plurality of pixel data utilizing said transform matrix, producing a partially transformed plurality of pixel data, is operable to write said partially transformed plurality of pixel data directly in a transposed manner to said internal register as transposed plurality of pixel data to save processor cycles, is operable to perform a 1-D transform of said transposed plurality of pixel data utilizing said transform matrix, producing a Hadamard transformed plurality of pixel data and is operable to write said Hadamard transformed plurality of pixel data directly in a transposed manner to said internal register to save processor cycles.
5 more elements
Dependencies are inferred from the claim text.