Layout of memory cells and input/output circuitry in a semiconductor memory device

A semiconductor memory device comprising:

• first and second memory cell arrays, each of the first and second memory cell arrays are arranged into a plurality of subarrays having rows and columns;
• a first pad column that is formed between the first and second memory cell arrays and comprises a plurality of first pads, the first pads arranged to be substantially parallel to a first direction at a first interval, such that a second interval between two of the first pads and located in a middle section of the first pad column is larger than the first interval;
• a second pad column that is located adjacent the first memory cell array and opposite the first pad column and comprises a plurality of second pads, the second pads arranged to be substantially parallel to the first direction at a third interval, such that a fourth interval between two of the second pads and located in a middle section of the second pad column is larger than the third interval;
• a plurality of circuits that are located between the first and second memory cell arrays and arranged to be substantially parallel to the first direction;
• and
• a plurality of lines, each being provided to connect between a respective one of the second pads and a corresponding one of the circuits,
• wherein a first distance between the first pad column and the second pad column is longer than a second distance between the circuits and the second pad column.