Memory device power control

An apparatus comprising:

• a first set of transistors including a first transistor and a second transistor, gates of the first and second transistors to couple to a first supply voltage, and a source or a drain of the first transistor coupled to at least one diode to couple to a second supply voltage, the first supply voltage to power on a first circuit of a memory device and having a first voltage range and the second supply voltage to power on a second circuit of the memory device and having a second voltage range different from the first voltage range;
• a second set of transistors including a third transistor and a fourth transistor, gates of the third and fourth transistors coupled to one or more of the first set of transistors, a source or a drain of the third transistor coupled to at least one leaker to couple to the second supply voltage, and a source or a drain of the fourth transistor to couple to an outcome signal, the outcome signal to be generated responsive to a voltage within the second voltage range and indicating whether the first supply voltage reaches a threshold voltage to power on the first circuit;
• and
• one or more transistors including a fifth transistor, a gate of the fifth transistor coupled to the at least one leaker and the source or the drain of the third transistor.