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US 8,787,106 B2Granted
Data storing circuit and repair circuit of memory device including the same
AssigneeSK hynix Inc.
InventorJeongsu Jeong
Life of this patent
Estimating the term…
Abstract
A data storing circuit includes: a storage unit configured to store a multi-bit data and a validity signal representing validity of the data; and a decision unit configured to determine validity of the multi-bit data by comparing one-bit data of the multi-bit data with the validity signal.
Claims13
A data storing circuit, comprising:
- a storage unit configured to store a multi-bit data and a validity signal representing validity of the data;
- and
- a decision unit configured to determine validity of the multi-bit data by comparing one-bit data of the multi-bit data with the validity signal.
A repair circuit of a memory device, comprising:
- a storage unit configured to store a multi-bit repair address and a validity signal representing validity of the repair address;
- a decision unit configured to determine validity of the repair address by comparing one-bit data of the multi-bit repair address with the validity signal and generate a validity determination signal in response to the comparison;
- a latch unit configured to store the validity determination signal and the repair address;
- and
- an address comparison unit configured to generate, when the validity determination signal is enabled, a repair signal by comparing an input address and the repair address stored in the latch unit.
2 more elements
An integrated circuit chip, comprising:
- an e-fuse array configured to store a plurality of data sets, each of which includes a multi-bit data, and validity signals that correspond to the data sets, respectively, and output a data set of the data sets and the corresponding validity signal at each cycle of a clock;
- a decision unit configured to generate validity determination signals, wherein the validity determination signals are each generated by comparing a respective one of the validity signals with one-bit data of the data set corresponding to the validity signal;
- a bus configured to transfer the validity determination signals and the data sets corresponding to the validity determination signals;
- a selection signal generation unit configured to generate a plurality of selection signals in response to the clock;
- and
- a plurality of latch sets configured to each store, in response to an enabled one of the selection signals, one of the validity determination signals and the data set corresponding to the validity determination signal.
3 more elements
Dependencies are inferred from the claim text.