Analog-to-digital and digital-to-analog conversion window adjustment based on reference cells in a memory device

A storage system comprising:

• a plurality of memory cells, the plurality of memory cells further comprising:
• a first pair of reference memory cells comprising a first reference memory cell for storing a first reference voltage and a second reference memory cell for storing a second reference voltage, wherein the first pair of reference memory cells are used to define an upper limit;
• and
• a second pair of reference memory cells comprising a third reference memory cell for storing a third reference voltage and a fourth reference memory cell for storing a fourth reference voltage, wherein the second pair of reference memory cells are used to define a lower limit;
• a buffer circuit to buffer the upper limit and lower limit;
• an analog-to-digital converter coupled to the memory array and the pair of reference memory cells, the analog-to-digital converter using the upper limit for a conversion window and the buffered lower limit for the conversion window such that the conversion window defines limits of a conversion process on each analog voltage wherein the conversion window is configured to move with a temperature of the plurality of memory cells.

A method for adjusting a conversion window, the method comprising:

• programming, at a predetermined temperature, a first reference voltage to a first reference cell, in a plurality of memory cells, that is configured to track a temperature of the plurality of memory cells;
• programming, at the predetermined temperature, a second reference voltage to a second reference cell, in the plurality of memory cells, that is configured to track the temperature of the plurality of memory cells, wherein the second reference voltage is different than the first reference voltage;
• programming a third reference voltage to a third reference memory cell, in the memory array, that is configured to track a temperature of the plurality of memory cells;
• programming a fourth reference voltage to a fourth reference memory cell, in the plurality of memory cells, that is configured to track a temperature of the plurality of memory cells;
• receiving a plurality of reference voltages;
• defining an upper limit based upon a first group of reference voltages from at least two of the first, second, third, and fourth reference memory cells;
• defining a lower limit based upon a second group of reference voltages from at least two of the first, second, third, and fourth reference memory cells, wherein the second group is different than the first group;
• and
• defining the conversion window in response to the upper limit and the lower limit.

A memory system comprising:

• a plurality of non-volatile memory cells;
• a first reference memory cell for storing a first reference voltage, the first reference memory cell further configured to track a temperature of the memory array;
• a second reference memory cell for storing a second reference voltage different than the first reference voltage, the second reference memory cell further configured to track a temperature of the memory array;
• a third reference memory cell for storing a third reference voltage, the third reference memory cell further configured to track a temperature of the memory array;
• a fourth reference memory cell for storing a fourth reference voltage, the fourth reference memory cell further configured to track a temperature of the memory array;
• wherein a first group of at least two of the first, second, third, and fourth reference memory cells are used to define an upper limit, wherein a second group of at least two of the first, second, third, and fourth reference memory cells are used to define a lower limit, wherein the second group uses different reference memory cells than the first group;
• a buffer circuit to buffer the upper limit and lower limit;
• and
• an analog-to-digital converter circuit, coupled to the plurality of memory cells and configured to convert an analog voltage from at least one of the plurality of memory cells to a digital bit pattern representative of the analog voltage in response to an analog-to-digital conversion window formed by the buffered upper limit and the buffered lower limit, such that an analog-to-digital conversion window moves with the temperature of the memory array.