Memory device and signal processing circuit

A semiconductor device comprising:

• cells arranged in matrix of m rows and n columns, the cells each comprising:
• a logic circuit configured to store data, the logic circuit including a first node and a second node;
• a first circuit electrically connected to the first node;
• a second circuit electrically connected to the second node;
• and
• a precharge circuit electrically connected to the first node, the second node, the first circuit, and the second circuit,
• wherein the first circuit and the second circuit each include a transistor comprising an oxide semiconductor film having low off-state current and a capacitor, and
• wherein off-state current density of the transistor having the low off-state current is less than or equal to 100 zA/μm.

A memory device comprising:

• memory cells arranged in matrix of m rows and n columns, the memory cells each comprising:
• a logic circuit configured to store data, the logic circuit including a first node and a second node;
• a first memory circuit electrically connected to the first node;
• a second memory circuit electrically connected to the second node;
• and
• a precharge circuit electrically connected to the first node, the second node, the first memory circuit, and the second memory circuit,
• wherein the first memory circuit and the second memory circuit each include a transistor comprising an oxide semiconductor film having low off-state current and a capacitor, and
• wherein off-state current density of the transistor having the low off-state current is less than or equal to 100 zA/μm.