Circuit design technique for DQS enable/disable calibration

A method for calibrating timing, the method comprising:

• receiving, at a gating circuit, a DQS enable/disable signal;
• providing, using a sampling circuit, an amount of delay;
• calibrating, using the gating circuit, the DQS enable/disable signal based on the amount of delay;
• outputting, using the gating circuit, a calibrated DQS enable/disable signal;
• and
• maintaining the timing of the calibrated DQS enable/disable signal over a plurality of clock cycles, using a delay chain tracking circuit, wherein the delay chain tracking circuit is coupled to the gating circuit and the sampling circuit.

A system for calibrating timing, the system comprising:

• a first circuit for providing an amount of delay;
• a second circuit for:
• receiving an input signal;
• signal generating a calibrated signal based on the amount of delay by calibrating timing of the input signal such that a falling edge of the calibrated signal is aligned with a rising edge of an input DQS signal;
• and
• outputting the calibrated signal;
• and
• a third circuit, coupled to the first circuit and the second circuit, for maintaining the timing of the calibrated signal over a plurality of clock cycles.