Soft erase operation for 3D non-volatile memory with selective inhibiting of passed bits

A method for performing an erase operation in a 3D stacked non-volatile memory device, comprising:

• performing an erase iteration of the erase operation for a set of memory cells, the set of memory cells comprises a first subset of memory cells in communication with a common select gate drain line;
• after the erase iteration, performing a verify test for the set of memory cells;
• and
• independently inhibiting the first subset of memory cells from being erased in a remainder of the erase operation if the first subset of memory cells meets a respective verify condition in the verify test, the remainder of the erase operation comprises an erase portion of a subsequent erase iteration of the erase operation, the independently inhibiting comprises setting the common select gate drain line at a voltage which inhibits erase of the first subset of memory cells during the erase portion of the subsequent erase iteration of the erase operation.

A 3D stacked non-volatile memory device, comprising:

• a plurality of word lines comprising conductive material, the conductive material alternates with dielectric material in a stack;
• a plurality of NAND strings, each NAND string comprising a set of memory cells and a select gate drain transistor at a drain-side end of the NAND string, a first subset of memory cells of the set of memory cells comprises one memory cell of each NAND string in communication with a common word line of the plurality of word lines;
• a set of bit lines in communication with the drain-side ends of the NAND strings;
• a set of select gate drain lines in communication with the select gate drain transistors of the NAND strings;
• and
• a control circuit, the control circuit:
• performs an erase iteration of an erase operation for the set of memory cells,
• after the erase iteration, performs a verify test for the set of memory cells,
• inhibits the first subset of memory cells from being erased in a remainder of the erase operation if the first subset of memory cells meets a respective verify condition in the verify test, the remainder of the erase operation comprises an erase portion of a subsequent erase iteration of the erase operation, and
• to independently inhibit the first subset of memory cells from being erased, floats a voltage of the common word line during the erase portion of the subsequent erase iteration of the erase operation.

A 3D stacked non-volatile memory device, comprising:

• a plurality of word lines comprising conductive material, the conductive material alternates with dielectric material in a stack;
• a plurality of NAND strings, each NAND string comprising a set of memory cells and a select gate drain transistor at a drain-side end of the NAND string,
• a set of bit lines in communication with the drain-side ends of the NAND strings;
• a set of select gate drain lines in communication with the select gate drain transistors of the NAND strings, a first subset of memory cells of the set of memory cells comprises one memory cell of each NAND string in communication with a common select gate drain line of the set of select gate drain lines;
• and
• a control circuit, the control circuit:
• performs an erase iteration of an erase operation for the set of memory cells,
• after the erase iteration, performs a verify test for the set of memory cells,
• independently inhibits the first subset of memory cells from being erased in a remainder of the erase operation if the first subset of memory cells meets a respective verify condition in the verify test, the remainder of the erase operation comprises an erase portion of a subsequent erase iteration of the erase operation, and
• to independently inhibit the first subset of memory cells from being erased, sets the common select gate drain line at a voltage which inhibits erase of the first subset of memory cells during the erase portion of the subsequent erase iteration of the erase operation.