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US 8,787,090 B2Granted
Memory cell operation
AssigneeMicron Technology, Inc.
InventorsAkira Goda, Seiichi Aritome
Life of this patent
Estimating the term…
Abstract
Embodiments of the present disclosure provide methods, devices, modules, and systems for programming memory cells. One method includes determining a quantity of erase pulses used to place a group of memory cells of the array in an erased state, and adjusting at least one operating parameter associated with programming the group of memory cells at least partially based on the determined quantity of erase pulses.
Claims20
A memory device comprising:
- an array of memory cells;
- and
- a controller coupled to the array and configured to:
- track a quantity of erase pulses used to place a number of memory cells of the array in an erased state;
- and
- adjust at least one operating parameter associated with programming the number of memory cells at a number of particular intervals based, at least partially, on the quantity of erase pulses;
- and
- wherein the at least one operating parameter includes at least one of:
- a program start voltage;
- a program step voltage;
- and
- a pass-through voltage.
9 more elements
A memory device comprising:
- an array of memory cells;
- and
- a controller coupled to the array and configured to:
- determine a quantity of erase pulses used to place a number of memory cells of the array in an erased state;
- and
- adjust, from an initial level to one of at least two different adjusted levels, at least one operating parameter associated with programming the number of memory cells based, at least partially, on the quantity of erase pulses;
- wherein a first of the at least two different adjusted levels corresponds to a first threshold quantity of erase pulses and a second of the at least two different adjusted levels corresponds to a second threshold quantity of erase pulses;
- and
- wherein the at least one operating parameter includes at least one of:
- a program start voltage;
- a program step voltage;
- and
- a pass-through voltage.
10 more elements
A method for operating an array of memory cells, the method comprising:
- determining a quantity of erase pulses used to place a group of memory cells of the array in an erased state;
- and
- adjusting, from an initial level to an adjusted level, at least one operating parameter associated with programming the group of memory cells at least partially based on the quantity of erase pulses;
- wherein the at least one operating parameter includes at least one of:
- a program start voltage;
- a program step voltage;
- and
- a pass-through voltage.
5 more elements
A method for operating an array of memory cells, the method comprising:
- counting a quantity of erase pulses used to place a number of memory cells of the array in an erased state;
- and
- changing, from an initial voltage to an adjusted voltage, at least one operating voltage associated with programming the number of memory cells based, at least partially, on the quantity of erase pulses;
- and
- wherein the at least one operating voltage includes at least one of:
- a program start voltage;
- a program step voltage;
- and
- a pass-through voltage.
6 more elements
Dependencies are inferred from the claim text.