Semiconductor memory device controlling operation timing of the sense circuit
AssigneeKabushiki Kaisha Toshiba
InventorTakashi Maeda
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AssigneeKabushiki Kaisha Toshiba
InventorTakashi Maeda
Estimating the term…
According to one embodiment, a semiconductor memory device includes a memory cell array, a bit line, a source line, and a sense circuit. The memory cell array includes memory strings which include memory cells connected in series and stacked above a semiconductor substrate. The bit line is coupled to one of the memory strings and is capable of transferring data. The source line is coupled to one of the memory strings. When data is read, a read current flows from a bit line into the source line. The sense circuit is coupled to the bit line and senses read data. An operation timing of the sense circuit is determined on the basis of a current flowing through the source line.
A semiconductor memory device comprising:
A method of reading data from a semiconductor memory device including a plurality of memory strings including memory cells connected in series and stacked above a semiconductor substrate, the method comprising:
Dependencies are inferred from the claim text.