Inhibiting address transitions in unselected memory banks of solid state memory circuits
AssigneeArizona Board of Regents for and on behalf of Arizona State University
InventorsLawrence T. Clark, Giby Samson
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Abstract
The present disclosure relates to inhibiting address transitions in unselected memory banks of solid state memory circuits. Bank selection and address gating circuitry may be used to provide a set of gated address signals to decode circuitry for each memory bank, such that the gated address signals associated with unselected memory banks are prevented from transitioning and the gated address signals associated with a selected memory bank are based on clocking in the status of address signals provided by memory control circuitry.
Claims20
A system comprising:
- solid state memory circuitry comprising a plurality of memory banks, which are associated with a plurality of memory accesses, and adapted to receive a plurality of sets of gated address signals, such that each set of gated address signals is associated with a corresponding one of the plurality of memory banks;
- and
- bank selection and address gating circuitry adapted to:
- during each memory access,
- receive a first clock signal having:
- a first phase;
- a second phase following the first phase;
- and
- a first transition at the end of the first phase and at the beginning of the second phase;
- receive a first plurality of address signals, which are stable during the first transition;
- and
- provide the plurality of sets of gated address signals, such that:
- each gated address signal of the plurality of sets of gated address signals does not transition during the first phase;
- one of the plurality of sets of gated address signals is associated with a selected one of the plurality of memory banks and is based on the first plurality of address signals during the first transition;
- and
- a balance of the plurality of sets of gated address signals is associated with unselected memory banks, such that each gated address signal of the balance of the plurality of sets of gated address signals is prevented from transitioning;
- wherein the one of the plurality of sets of gated address signals provides an address associated with the each memory access.
A method comprising:
- receiving a plurality of sets of gated address signals, such that each set of gated address signals is associated with a corresponding one of a plurality of memory banks, which are associated with a plurality of memory accesses;
- receiving a first clock signal having:
- a first phase;
- a second phase following the first phase;
- and
- a first transition at the end of the first phase and at the beginning of the second phase;
- receiving a first plurality of address signals, which are stable during the first transition;
- and
- providing the plurality of sets of gated address signals, such that:
- each gated address signal of the plurality of sets of gated address signals does not transition during the first phase;
- one of the plurality of sets of gated address signals is associated with a selected one of the plurality of memory banks and is based on the first plurality of address signals during the first transition;
- and
- a balance of the plurality of sets of gated address signals is associated with unselected memory banks, such that each gated address signal of the balance of the plurality of sets of gated address signals is prevented from transitioning;
- wherein the one of the plurality of sets of gated address signals provides an address associated with the each memory access.
Dependencies are inferred from the claim text.